[llvm] Support replacing `add rd, Zero, Zero` with `c.li rd, 0` (PR #86937)

[Mark Goncharov via llvm-commits]

mga-sc wrote:

> I agree that having this replacement makes sense. Whether the pattern realistically comes from codegen or not doesn't matter, because the RISC-V assembler should opportunistically replace user-written 32-bit instructions with compressed ones whenever possible. With that in mind, I think the .ll test case with inline asm isn't a very useful way to test this and it would be better to just test it at MC layer only in llvm/test/MC/RISCV/compress-rv32i.s.

Done

https://github.com/llvm/llvm-project/pull/86937