[llvm] Feature tablegen hwmode bitset access (PR #88377)

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git-clang-format --diff cca30dfb5935e05837e37cced4407a63393c6642 53f655dd2b3a09839786a862ba20380149ccbe4d -- llvm/include/llvm/MC/MCSubtargetInfo.h llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCVSubtarget.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/utils/TableGen/CodeEmitterGen.cpp llvm/utils/TableGen/Common/CodeGenHwModes.cpp llvm/utils/TableGen/SubtargetEmitter.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 7298526bb3..caf2f1c638 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -640,8 +640,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   TRY_TO_DECODE_FEATURE(
       RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
       "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
-  TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureEncodingTmp), DecoderTable_EncodingTmp16,
-                           "For HwMode check");
+  TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureEncodingTmp),
+                           DecoderTable_EncodingTmp16, "For HwMode check");
   TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
                            "RISCV_C table (16-bit Instruction)");
 

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https://github.com/llvm/llvm-project/pull/88377