[llvm] [SelectionDAG] Propogate Disjoint flag. (PR #88370)

[via llvm-commits]

https://github.com/fengfeng09 created https://github.com/llvm/llvm-project/pull/88370

None

>From 12e66b2741d51c6ddb219b59b3f35040ad571df8 Mon Sep 17 00:00:00 2001
From: "feng.feng" <feng.feng at iluvatar.com>
Date: Thu, 11 Apr 2024 15:18:31 +0800
Subject: [PATCH] [SelectionDAG] Propogate Disjoint flag.

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp    | 2 ++
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8fe074666a3dc9..59ef66fba73164 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9530,6 +9530,8 @@ static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) {
   SDValue ShiftSumC = DAG.getConstant(*C0Val + C1Val, DL, ShiftAmtVT);
   SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSumC);
   SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, C1);
+  // Propogate flags.
+  SelectionDAG::FlagInserter FlagsInserter(DAG, LogicOp->getFlags());
   return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2);
 }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 409d66adfd67d1..dd5c3d741aa7dc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -544,6 +544,8 @@ bool TargetLowering::ShrinkDemandedConstant(SDValue Op,
     if (!C.isSubsetOf(DemandedBits)) {
       EVT VT = Op.getValueType();
       SDValue NewC = TLO.DAG.getConstant(DemandedBits & C, DL, VT);
+      // Propogate flags.
+      SelectionDAG::FlagInserter FlagsInserter(TLO.DAG, Op->getFlags());
       SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
       return TLO.CombineTo(Op, NewOp);
     }