[llvm] 9c6e54b - [AArch64] Fix to Neoverse V2 scheduling model (#88130)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 11 01:32:21 PDT 2024
Author: Maciej Gabka
Date: 2024-04-11T09:32:17+01:00
New Revision: 9c6e54b154cbbb7da0f45b4ae1e66bcf492151f1
URL: https://github.com/llvm/llvm-project/commit/9c6e54b154cbbb7da0f45b4ae1e66bcf492151f1
DIFF: https://github.com/llvm/llvm-project/commit/9c6e54b154cbbb7da0f45b4ae1e66bcf492151f1.diff
LOG: [AArch64] Fix to Neoverse V2 scheduling model (#88130)
The size of ROB was incorrecty copied from the Neoverse N2, while it has
actually higher value as descibed in
https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/arm-neoverse-v2-platform-best-in-class-cloud-and-ai-ml-performance
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 4d7f44e7b9b9ab..7fed8fed900171 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -15,7 +15,7 @@
def NeoverseV2Model : SchedMachineModel {
let IssueWidth = 16; // Micro-ops dispatched at a time.
- let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2.
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
let LoadLatency = 4; // Optimistic load latency.
let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
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