[llvm] 053750c - [PowerPC] Fix the undef register for VECINSERT

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2024-04-11T04:01:07-04:00
New Revision: 053750c3b42c126eb4620f62cbf4e665803b941d

URL: https://github.com/llvm/llvm-project/commit/053750c3b42c126eb4620f62cbf4e665803b941d
DIFF: https://github.com/llvm/llvm-project/commit/053750c3b42c126eb4620f62cbf4e665803b941d.diff

LOG: [PowerPC] Fix the undef register for VECINSERT

If the V2 of the vector_shuffle is undef, the two vector inputs are
expected to be the same when do the VECINSERT transformation. For now
the first operand of VECINSERT is set to undef which is not right.
This patch fixes this bug.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/test/CodeGen/PowerPC/xxinsertw.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 43e4a34a9b3483..52d5b713670595 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10142,7 +10142,9 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
   if (Subtarget.hasP9Vector() &&
       PPC::isXXINSERTWMask(SVOp, ShiftElts, InsertAtByte, Swap,
                            isLittleEndian)) {
-    if (Swap)
+    if (V2.isUndef())
+      V2 = V1;
+    else if (Swap)
       std::swap(V1, V2);
     SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
     SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2);

diff  --git a/llvm/test/CodeGen/PowerPC/xxinsertw.ll b/llvm/test/CodeGen/PowerPC/xxinsertw.ll
index b48eac06a694ad..f944b5a175be44 100644
--- a/llvm/test/CodeGen/PowerPC/xxinsertw.ll
+++ b/llvm/test/CodeGen/PowerPC/xxinsertw.ll
@@ -24,8 +24,7 @@ define <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) {
   ; CHECK-NEXT:   [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]]
   ; CHECK-NEXT:   [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG 1, killed [[MTVSRWZ2]], %subreg.sub_64
   ; CHECK-NEXT:   [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]]
-  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vsrc = IMPLICIT_DEF
-  ; CHECK-NEXT:   [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[DEF]], killed [[XXPERM]], 8
+  ; CHECK-NEXT:   [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[XXPERM]], [[XXPERM]], 8
   ; CHECK-NEXT:   $v2 = COPY [[XXINSERTW]]
   ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $v2
   %1 = insertelement <4 x i1> poison, i1 %c1, i64 0