[llvm] 2fdfea0 - [AMDGPU] Add v2i32 to the VS_64 types. NFCI. (#88318)
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Wed Apr 10 14:50:57 PDT 2024
Author: Stanislav Mekhanoshin
Date: 2024-04-10T14:50:54-07:00
New Revision: 2fdfea088c8d78119b74116b94bc6729ce0e3efe
URL: https://github.com/llvm/llvm-project/commit/2fdfea088c8d78119b74116b94bc6729ce0e3efe
DIFF: https://github.com/llvm/llvm-project/commit/2fdfea088c8d78119b74116b94bc6729ce0e3efe.diff
LOG: [AMDGPU] Add v2i32 to the VS_64 types. NFCI. (#88318)
I am trying to use VOP3Inst with intrinsic taking v2i32 operand and it
fails to create patterm without it.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 04f3a2f5760532..d6d49889656bbc 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2087,7 +2087,7 @@ def : GCNPat <
def : GCNPat <
(DivergentUnaryFrag<fneg> (v2f32 VReg_64:$src)),
(V_PK_ADD_F32 11 /* OP_SEL_1 | NEG_LO | HEG_HI */, VReg_64:$src,
- 11 /* OP_SEL_1 | NEG_LO | HEG_HI */, 0,
+ 11 /* OP_SEL_1 | NEG_LO | HEG_HI */, (i64 0),
0, 0, 0, 0, 0)
> {
let SubtargetPredicate = HasPackedFP32Ops;
@@ -2999,7 +2999,7 @@ def : GCNPat<
let SubtargetPredicate = HasPackedFP32Ops in {
def : GCNPat<
(fcanonicalize (v2f32 (VOP3PMods v2f32:$src, i32:$src_mods))),
- (V_PK_MUL_F32 0, CONST.FP32_ONE, $src_mods, $src)
+ (V_PK_MUL_F32 0, (i64 CONST.FP32_ONE), $src_mods, $src)
>;
}
@@ -3007,7 +3007,7 @@ def : GCNPat<
let SubtargetPredicate = isNotGFX12Plus in {
def : GCNPat<
(fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))),
- (V_MUL_F64_e64 0, CONST.FP64_ONE, $src_mods, $src)
+ (V_MUL_F64_e64 0, (i64 CONST.FP64_ONE), $src_mods, $src)
>;
}
} // End AddedComplexity = -5
@@ -3369,7 +3369,7 @@ def : GCNPat <
SRCMODS.NONE,
(V_FRACT_F64_e64 $mods, $x),
SRCMODS.NONE,
- (V_MOV_B64_PSEUDO 0x3fefffffffffffff)),
+ (V_MOV_B64_PSEUDO (i64 0x3fefffffffffffff))),
$x,
(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, (i32 3 /*NaN*/))))
>;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index cb6591bf624494..01ed565bb756dd 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1046,7 +1046,7 @@ def VS_32_Lo128 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2
let HasSGPR = 1;
}
-def VS_64 : SIRegisterClass<"AMDGPU", [i64, f64, v2f32], 32, (add VReg_64, SReg_64)> {
+def VS_64 : SIRegisterClass<"AMDGPU", VReg_64.RegTypes, 32, (add VReg_64, SReg_64)> {
let isAllocatable = 0;
let HasVGPR = 1;
let HasSGPR = 1;
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