[llvm] 4dcf33b - [AArch64] Cleanup and GISel coverage for lrint tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 10 10:14:03 PDT 2024
Author: David Green
Date: 2024-04-10T18:13:57+01:00
New Revision: 4dcf33b6c2806216dfe8c5e1e3582a45516dbc69
URL: https://github.com/llvm/llvm-project/commit/4dcf33b6c2806216dfe8c5e1e3582a45516dbc69
DIFF: https://github.com/llvm/llvm-project/commit/4dcf33b6c2806216dfe8c5e1e3582a45516dbc69.diff
LOG: [AArch64] Cleanup and GISel coverage for lrint tests. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/lrint-conv.ll
llvm/test/CodeGen/AArch64/vector-lrint.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/lrint-conv.ll b/llvm/test/CodeGen/AArch64/lrint-conv.ll
index 80f1e8b8fc18e2..b61d6f04b400e0 100644
--- a/llvm/test/CodeGen/AArch64/lrint-conv.ll
+++ b/llvm/test/CodeGen/AArch64/lrint-conv.ll
@@ -1,64 +1,78 @@
-; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
-; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64 | FileCheck %s --check-prefixes=FALLBACK,CHECK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for testmswl
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsll
-; CHECK-LABEL: testmsws:
-; CHECK: frintx [[REG:s[0-9]]], s0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK: ret
-; FALLBACK-NOT: remark{{.*}}testmsws
define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs x0, s0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxs:
-; CHECK: frintx [[REG:s[0-9]]], s0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK-NEXT: ret
-; FALLBACK-NOT: remark{{.*}}testmsxs
define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx s0, s0
+; CHECK-NEXT: fcvtzs x0, s0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
ret i64 %0
}
-; CHECK-LABEL: testmswd:
-; CHECK: frintx [[REG:d[0-9]]], d0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK: ret
-; FALLBACK-NOT: remark{{.*}}testmswd
define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx d0, d0
+; CHECK-NEXT: fcvtzs x0, d0
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsxd:
-; CHECK: frintx [[REG:d[0-9]]], d0
-; CHECK-NEXT: fcvtzs x0, [[REG]]
-; CHECK-NEXT: ret
-; FALLBACK-NOT: remark{{.*}}testmsxd
define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: frintx d0, d0
+; CHECK-NEXT: fcvtzs x0, d0
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
ret i64 %0
}
-; CHECK-LABEL: testmswl:
-; CHECK: bl lrintl
define dso_local i32 @testmswl(fp128 %x) {
+; CHECK-LABEL: testmswl:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl lrintl
+; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
-; CHECK-LABEL: testmsll:
-; CHECK: b lrintl
define dso_local i64 @testmsll(fp128 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: b lrintl
entry:
%0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x)
ret i64 %0
diff --git a/llvm/test/CodeGen/AArch64/vector-lrint.ll b/llvm/test/CodeGen/AArch64/vector-lrint.ll
index 9c46cf69cb0bfc..b7fcd11ba8d164 100644
--- a/llvm/test/CodeGen/AArch64/vector-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/vector-lrint.ll
@@ -1,6 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=aarch64 -mattr=+neon | FileCheck %s
-; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=aarch64 -mattr=+neon | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for lrint_v1f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16i64_v16f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32i64_v32f16
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16i64_v16f32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f64
define <1 x i64> @lrint_v1f16(<1 x half> %x) {
; CHECK-LABEL: lrint_v1f16:
@@ -372,13 +386,20 @@ define <32 x i64> @lrint_v32i64_v32f16(<32 x half> %x) {
declare <32 x i64> @llvm.lrint.v32i64.v32f16(<32 x half>)
define <1 x i64> @lrint_v1f32(<1 x float> %x) {
-; CHECK-LABEL: lrint_v1f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: lrint_v1f32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: frintx s0, s0
+; CHECK-SD-NEXT: fcvtzs x8, s0
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: lrint_v1f32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: frintx s0, s0
+; CHECK-GI-NEXT: fcvtzs x8, s0
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%a = call <1 x i64> @llvm.lrint.v1i64.v1f32(<1 x float> %x)
ret <1 x i64> %a
}
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