[llvm] 5ae9ffb - [RISCV] Address review comment from 88062

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2024-04-10T07:21:41-07:00
New Revision: 5ae9ffbd18fd93edbbc8efebe140aeb24cd763c2

URL: https://github.com/llvm/llvm-project/commit/5ae9ffbd18fd93edbbc8efebe140aeb24cd763c2
DIFF: https://github.com/llvm/llvm-project/commit/5ae9ffbd18fd93edbbc8efebe140aeb24cd763c2.diff

LOG: [RISCV] Address review comment from 88062

As pointed out by Fraser, KillSrcReg is always false at this point in
code, and having the inconcistency on whether we check the flag between
the if and else blocks is confusing.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 46e79272d60eb3..84af6eec40ee6f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -210,8 +210,7 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
       unsigned Opc = NumOfVReg == 2 ? RISCV::SH1ADD :
         (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
       BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
-          .addReg(ScratchReg, RegState::Kill)
-          .addReg(SrcReg, getKillRegState(KillSrcReg))
+          .addReg(ScratchReg, RegState::Kill).addReg(SrcReg)
           .setMIFlag(Flag);
     } else {
       TII->mulImm(MF, MBB, II, DL, ScratchReg, NumOfVReg, Flag);