[compiler-rt] [RISCV] Support rv{32, 64}e in the compiler builtins (PR #88252)

Cyrill Leutwiler via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 10 03:37:18 PDT 2024


https://github.com/xermicus updated https://github.com/llvm/llvm-project/pull/88252

>From b0c7608ddec92b3ddf6488f95f8d4309c7ea433f Mon Sep 17 00:00:00 2001
From: xermicus <cyrill at parity.io>
Date: Wed, 10 Apr 2024 12:22:05 +0200
Subject: [PATCH 1/2] Support rv{32, 64}e in the compiler builtins: Register
 spills (save/restore) In RISC-V embedded work differently because there are
 less registers and different stack alignment.

Signed-off-by: xermicus <cyrill at parity.io>
---
 compiler-rt/lib/builtins/riscv/restore.S | 42 ++++++++++++++++++++++++
 compiler-rt/lib/builtins/riscv/save.S    | 42 ++++++++++++++++++++++++
 2 files changed, 84 insertions(+)

diff --git a/compiler-rt/lib/builtins/riscv/restore.S b/compiler-rt/lib/builtins/riscv/restore.S
index 73f64a920d6698..6f43842c8ca684 100644
--- a/compiler-rt/lib/builtins/riscv/restore.S
+++ b/compiler-rt/lib/builtins/riscv/restore.S
@@ -22,6 +22,8 @@
 
 #if __riscv_xlen == 32
 
+#ifndef __riscv_32e
+
   .globl  __riscv_restore_12
   .type   __riscv_restore_12, at function
 __riscv_restore_12:
@@ -86,8 +88,29 @@ __riscv_restore_0:
   addi    sp, sp, 16
   ret
 
+#else
+
+  .globl  __riscv_restore_2
+  .type   __riscv_restore_2, at function
+  .globl  __riscv_restore_1
+  .type   __riscv_restore_1, at function
+  .globl  __riscv_restore_0
+  .type   __riscv_restore_0, at function
+__riscv_restore_2:
+__riscv_restore_1:
+__riscv_restore_0:
+  lw      s1,  0(sp)
+  lw      s0,  4(sp)
+  lw      ra,  8(sp)
+  addi    sp, sp, 12
+  ret
+
+#endif
+
 #elif __riscv_xlen == 64
 
+#ifndef __riscv_64e
+
   .globl  __riscv_restore_12
   .type   __riscv_restore_12, at function
 __riscv_restore_12:
@@ -161,6 +184,25 @@ __riscv_restore_0:
   addi    sp, sp, 16
   ret
 
+#else
+
+  .globl  __riscv_restore_2
+  .type   __riscv_restore_2, at function
+  .globl  __riscv_restore_1
+  .type   __riscv_restore_1, at function
+  .globl  __riscv_restore_0
+  .type   __riscv_restore_0, at function
+__riscv_restore_2:
+__riscv_restore_1:
+__riscv_restore_0:
+  ld      s1,  0(sp)
+  ld      s0,  8(sp)
+  ld      ra,  16(sp)
+  addi    sp, sp, 24
+  ret
+
+#endif
+
 #else
 # error "xlen must be 32 or 64 for save-restore implementation
 #endif
diff --git a/compiler-rt/lib/builtins/riscv/save.S b/compiler-rt/lib/builtins/riscv/save.S
index 85501aeb4c2e93..e96fca535b1ffa 100644
--- a/compiler-rt/lib/builtins/riscv/save.S
+++ b/compiler-rt/lib/builtins/riscv/save.S
@@ -18,6 +18,8 @@
 
 #if __riscv_xlen == 32
 
+#ifndef __riscv_32e
+
   .globl  __riscv_save_12
   .type   __riscv_save_12, at function
 __riscv_save_12:
@@ -92,8 +94,29 @@ __riscv_save_0:
   sw      ra,  12(sp)
   jr      t0
 
+#else
+
+  .globl  __riscv_save_2
+  .type   __riscv_save_2, at function
+  .globl  __riscv_save_1
+  .type   __riscv_save_1, at function
+  .globl  __riscv_save_0
+  .type   __riscv_save_0, at function
+__riscv_save_2:
+__riscv_save_1:
+__riscv_save_0:
+  addi    sp, sp, -12
+  sw      s1,  0(sp)
+  sw      s0,  4(sp)
+  sw      ra,  8(sp)
+  jr      t0
+
+#endif
+
 #elif __riscv_xlen == 64
 
+#ifndef __riscv_64e
+
   .globl  __riscv_save_12
   .type   __riscv_save_12, at function
 __riscv_save_12:
@@ -181,6 +204,25 @@ __riscv_save_0:
   sd     ra, 8(sp)
   jr     t0
 
+#else
+
+  .globl  __riscv_save_2
+  .type   __riscv_save_2, at function
+  .globl  __riscv_save_1
+  .type   __riscv_save_1, at function
+  .globl  __riscv_save_0
+  .type   __riscv_save_0, at function
+__riscv_save_2:
+__riscv_save_1:
+__riscv_save_0:
+  addi   sp, sp, -24
+  sd     s0, 0(sp)
+  sd     s1, 8(sp)
+  sd     ra, 16(sp)
+  jr     t0
+
+#endif
+
 #else
 # error "xlen must be 32 or 64 for save-restore implementation
 #endif

>From 7030c29c88b24ebd1aabc06f3211c1c1a1ade686 Mon Sep 17 00:00:00 2001
From: xermicus <cyrill at parity.io>
Date: Wed, 10 Apr 2024 12:37:01 +0200
Subject: [PATCH 2/2] typo

Signed-off-by: xermicus <cyrill at parity.io>
---
 compiler-rt/lib/builtins/riscv/save.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/compiler-rt/lib/builtins/riscv/save.S b/compiler-rt/lib/builtins/riscv/save.S
index e96fca535b1ffa..3e044179ff7f1d 100644
--- a/compiler-rt/lib/builtins/riscv/save.S
+++ b/compiler-rt/lib/builtins/riscv/save.S
@@ -216,8 +216,8 @@ __riscv_save_2:
 __riscv_save_1:
 __riscv_save_0:
   addi   sp, sp, -24
-  sd     s0, 0(sp)
-  sd     s1, 8(sp)
+  sd     s1, 0(sp)
+  sd     s0, 8(sp)
   sd     ra, 16(sp)
   jr     t0
 



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