[llvm] [AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for bit-twiddling. (PR #83514)

Dinar Temirbulatov via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 10 03:08:09 PDT 2024

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https://github.com/dtemirbulatov closed https://github.com/llvm/llvm-project/pull/83514

Previous message: [llvm] [AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for bit-twiddling. (PR #83514)
Next message: [llvm] [DAG] Prevent combination on small negative value for vscale (PR #88108)
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