[llvm] 6c40d46 - [X86] Use `nneg` flag when trying to convert `uitofp` -> `sitofp`

[Noah Goldstein via llvm-commits]

Author: Noah Goldstein
Date: 2024-04-09T23:06:55-05:00
New Revision: 6c40d463c28e7a6843bea9f6d838cd89e586cbe8

URL: https://github.com/llvm/llvm-project/commit/6c40d463c28e7a6843bea9f6d838cd89e586cbe8
DIFF: https://github.com/llvm/llvm-project/commit/6c40d463c28e7a6843bea9f6d838cd89e586cbe8.diff

LOG: [X86] Use `nneg` flag when trying to convert `uitofp` -> `sitofp`

Closes #86694

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/uint_to_fp.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5405c2921e5188..010f9c30ab4033 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54126,7 +54126,8 @@ static SDValue combineUIntToFP(SDNode *N, SelectionDAG &DAG,
   // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
   // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
   // the optimization here.
-  if (DAG.SignBitIsZero(Op0)) {
+  SDNodeFlags Flags = N->getFlags();
+  if (Flags.hasNonNeg() || DAG.SignBitIsZero(Op0)) {
     if (IsStrict)
       return DAG.getNode(ISD::STRICT_SINT_TO_FP, SDLoc(N), {VT, MVT::Other},
                          {N->getOperand(0), Op0});

diff  --git a/llvm/test/CodeGen/X86/uint_to_fp.ll b/llvm/test/CodeGen/X86/uint_to_fp.ll
index 8b9dfedb8da02f..8c8cbb151974d6 100644
--- a/llvm/test/CodeGen/X86/uint_to_fp.ll
+++ b/llvm/test/CodeGen/X86/uint_to_fp.ll
@@ -52,10 +52,7 @@ define float @test_with_nneg(i32 %x) nounwind {
 ; X86-LABEL: test_with_nneg:
 ; X86:       ## %bb.0:
 ; X86-NEXT:    pushl %eax
-; X86-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT:    orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-NEXT:    cvtsd2ss %xmm0, %xmm0
+; X86-NEXT:    cvtsi2ssl {{[0-9]+}}(%esp), %xmm0
 ; X86-NEXT:    movss %xmm0, (%esp)
 ; X86-NEXT:    flds (%esp)
 ; X86-NEXT:    popl %eax
@@ -63,8 +60,7 @@ define float @test_with_nneg(i32 %x) nounwind {
 ;
 ; X64-LABEL: test_with_nneg:
 ; X64:       ## %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    cvtsi2ss %rax, %xmm0
+; X64-NEXT:    cvtsi2ss %edi, %xmm0
 ; X64-NEXT:    retq
   %r = uitofp nneg i32 %x to float
   ret float %r
@@ -73,24 +69,12 @@ define float @test_with_nneg(i32 %x) nounwind {
 define <4 x float> @test_with_nneg_vec(<4 x i32> %x) nounwind {
 ; X86-LABEL: test_with_nneg_vec:
 ; X86:       ## %bb.0:
-; X86-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; X86-NEXT:    pand %xmm0, %xmm1
-; X86-NEXT:    por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
-; X86-NEXT:    psrld $16, %xmm0
-; X86-NEXT:    por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-NEXT:    subps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; X86-NEXT:    addps %xmm1, %xmm0
+; X86-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_with_nneg_vec:
 ; X64:       ## %bb.0:
-; X64-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; X64-NEXT:    pand %xmm0, %xmm1
-; X64-NEXT:    por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; X64-NEXT:    psrld $16, %xmm0
-; X64-NEXT:    por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT:    subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; X64-NEXT:    addps %xmm1, %xmm0
+; X64-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; X64-NEXT:    retq
   %r = uitofp nneg <4 x i32> %x to <4 x float>
   ret <4 x float> %r