[llvm] Add IIT_V6 to support 6-element vectors in intrinsics. (PR #88196)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 9 16:22:01 PDT 2024
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/88196
>From 64629a29d91c4f34e776802b2bd9875cd7ec71f5 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Tue, 9 Apr 2024 14:10:10 -0700
Subject: [PATCH 1/2] Add IIT_V6 to support 6-element vectors in intrinsics.
Needed for the future patch.
---
llvm/include/llvm/IR/Intrinsics.td | 45 +++++++++++++------------
llvm/lib/IR/Function.cpp | 4 +++
llvm/test/TableGen/intrinsic-varargs.td | 2 +-
3 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index f0723a633f0fc5..fcdef81a6679eb 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -272,28 +272,29 @@ def IIT_F32 : IIT_VT<f32, 7>;
def IIT_F64 : IIT_VT<f64, 8>;
def IIT_V2 : IIT_Vec<2, 9>;
def IIT_V4 : IIT_Vec<4, 10>;
-def IIT_V8 : IIT_Vec<8, 11>;
-def IIT_V16 : IIT_Vec<16, 12>;
-def IIT_V32 : IIT_Vec<32, 13>;
-def IIT_PTR : IIT_Base< 14>;
-def IIT_ARG : IIT_Base< 15>;
-
-def IIT_V64 : IIT_Vec<64, 16>;
-def IIT_MMX : IIT_VT<x86mmx, 17>;
-def IIT_TOKEN : IIT_VT<token, 18>;
-def IIT_METADATA : IIT_VT<MetadataVT, 19>;
-def IIT_EMPTYSTRUCT : IIT_VT<OtherVT, 20>;
-def IIT_STRUCT2 : IIT_Base<21>;
-def IIT_STRUCT3 : IIT_Base<22>;
-def IIT_STRUCT4 : IIT_Base<23>;
-def IIT_STRUCT5 : IIT_Base<24>;
-def IIT_EXTEND_ARG : IIT_Base<25>;
-def IIT_TRUNC_ARG : IIT_Base<26>;
-def IIT_ANYPTR : IIT_Base<27>;
-def IIT_V1 : IIT_Vec<1, 28>;
-def IIT_VARARG : IIT_VT<isVoid, 29>;
-def IIT_HALF_VEC_ARG : IIT_Base<30>;
-def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<31>;
+def IIT_V6 : IIT_Vec<6, 11>;
+def IIT_V8 : IIT_Vec<8, 12>;
+def IIT_V16 : IIT_Vec<16, 13>;
+def IIT_V32 : IIT_Vec<32, 14>;
+def IIT_PTR : IIT_Base< 15>;
+def IIT_ARG : IIT_Base< 16>;
+
+def IIT_V64 : IIT_Vec<64, 17>;
+def IIT_MMX : IIT_VT<x86mmx, 18>;
+def IIT_TOKEN : IIT_VT<token, 19>;
+def IIT_METADATA : IIT_VT<MetadataVT, 20>;
+def IIT_EMPTYSTRUCT : IIT_VT<OtherVT, 21>;
+def IIT_STRUCT2 : IIT_Base<22>;
+def IIT_STRUCT3 : IIT_Base<23>;
+def IIT_STRUCT4 : IIT_Base<24>;
+def IIT_STRUCT5 : IIT_Base<25>;
+def IIT_EXTEND_ARG : IIT_Base<26>;
+def IIT_TRUNC_ARG : IIT_Base<27>;
+def IIT_ANYPTR : IIT_Base<28>;
+def IIT_V1 : IIT_Vec<1, 29>;
+def IIT_VARARG : IIT_VT<isVoid, 30>;
+def IIT_HALF_VEC_ARG : IIT_Base<31>;
+def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<32>;
def IIT_VEC_OF_ANYPTRS_TO_ELT : IIT_Base<34>;
def IIT_I128 : IIT_Int<128, 35>;
def IIT_V512 : IIT_Vec<512, 36>;
diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp
index b5fda9bb3d129a..96953ac49c19b4 100644
--- a/llvm/lib/IR/Function.cpp
+++ b/llvm/lib/IR/Function.cpp
@@ -1172,6 +1172,10 @@ static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
OutputTable.push_back(IITDescriptor::getVector(4, IsScalableVector));
DecodeIITType(NextElt, Infos, Info, OutputTable);
return;
+ case IIT_V6:
+ OutputTable.push_back(IITDescriptor::getVector(6, IsScalableVector));
+ DecodeIITType(NextElt, Infos, Info, OutputTable);
+ return;
case IIT_V8:
OutputTable.push_back(IITDescriptor::getVector(8, IsScalableVector));
DecodeIITType(NextElt, Infos, Info, OutputTable);
diff --git a/llvm/test/TableGen/intrinsic-varargs.td b/llvm/test/TableGen/intrinsic-varargs.td
index 3634e16e205653..182b44da0b2698 100644
--- a/llvm/test/TableGen/intrinsic-varargs.td
+++ b/llvm/test/TableGen/intrinsic-varargs.td
@@ -3,5 +3,5 @@
include "llvm/IR/Intrinsics.td"
-// CHECK: /* 0 */ 0, 29, 0,
+// CHECK: /* 0 */ 0, 30, 0,
def int_foo : Intrinsic<[], [llvm_vararg_ty]>;
>From bbffabcb7072390ffc894d4fd3d99d5d7ae0342f Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Tue, 9 Apr 2024 15:21:59 -0700
Subject: [PATCH 2/2] Moved to the end of the enum.
---
llvm/include/llvm/IR/Intrinsics.td | 46 ++++++++++++-------------
llvm/test/TableGen/intrinsic-varargs.td | 2 +-
2 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index fcdef81a6679eb..bdd8465883fcff 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -272,29 +272,28 @@ def IIT_F32 : IIT_VT<f32, 7>;
def IIT_F64 : IIT_VT<f64, 8>;
def IIT_V2 : IIT_Vec<2, 9>;
def IIT_V4 : IIT_Vec<4, 10>;
-def IIT_V6 : IIT_Vec<6, 11>;
-def IIT_V8 : IIT_Vec<8, 12>;
-def IIT_V16 : IIT_Vec<16, 13>;
-def IIT_V32 : IIT_Vec<32, 14>;
-def IIT_PTR : IIT_Base< 15>;
-def IIT_ARG : IIT_Base< 16>;
-
-def IIT_V64 : IIT_Vec<64, 17>;
-def IIT_MMX : IIT_VT<x86mmx, 18>;
-def IIT_TOKEN : IIT_VT<token, 19>;
-def IIT_METADATA : IIT_VT<MetadataVT, 20>;
-def IIT_EMPTYSTRUCT : IIT_VT<OtherVT, 21>;
-def IIT_STRUCT2 : IIT_Base<22>;
-def IIT_STRUCT3 : IIT_Base<23>;
-def IIT_STRUCT4 : IIT_Base<24>;
-def IIT_STRUCT5 : IIT_Base<25>;
-def IIT_EXTEND_ARG : IIT_Base<26>;
-def IIT_TRUNC_ARG : IIT_Base<27>;
-def IIT_ANYPTR : IIT_Base<28>;
-def IIT_V1 : IIT_Vec<1, 29>;
-def IIT_VARARG : IIT_VT<isVoid, 30>;
-def IIT_HALF_VEC_ARG : IIT_Base<31>;
-def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<32>;
+def IIT_V8 : IIT_Vec<8, 11>;
+def IIT_V16 : IIT_Vec<16, 12>;
+def IIT_V32 : IIT_Vec<32, 13>;
+def IIT_PTR : IIT_Base< 14>;
+def IIT_ARG : IIT_Base< 15>;
+
+def IIT_V64 : IIT_Vec<64, 16>;
+def IIT_MMX : IIT_VT<x86mmx, 17>;
+def IIT_TOKEN : IIT_VT<token, 18>;
+def IIT_METADATA : IIT_VT<MetadataVT, 19>;
+def IIT_EMPTYSTRUCT : IIT_VT<OtherVT, 20>;
+def IIT_STRUCT2 : IIT_Base<21>;
+def IIT_STRUCT3 : IIT_Base<22>;
+def IIT_STRUCT4 : IIT_Base<23>;
+def IIT_STRUCT5 : IIT_Base<24>;
+def IIT_EXTEND_ARG : IIT_Base<25>;
+def IIT_TRUNC_ARG : IIT_Base<26>;
+def IIT_ANYPTR : IIT_Base<27>;
+def IIT_V1 : IIT_Vec<1, 28>;
+def IIT_VARARG : IIT_VT<isVoid, 29>;
+def IIT_HALF_VEC_ARG : IIT_Base<30>;
+def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<31>;
def IIT_VEC_OF_ANYPTRS_TO_ELT : IIT_Base<34>;
def IIT_I128 : IIT_Int<128, 35>;
def IIT_V512 : IIT_Vec<512, 36>;
@@ -320,6 +319,7 @@ def IIT_FUNCREF : IIT_VT<funcref, 55>;
def IIT_I2 : IIT_Int<2, 57>;
def IIT_I4 : IIT_Int<4, 58>;
def IIT_AARCH64_SVCOUNT : IIT_VT<aarch64svcount, 59>;
+def IIT_V6 : IIT_Vec<6, 60>;
}
defvar IIT_all_FixedTypes = !filter(iit, IIT_all,
diff --git a/llvm/test/TableGen/intrinsic-varargs.td b/llvm/test/TableGen/intrinsic-varargs.td
index 182b44da0b2698..3634e16e205653 100644
--- a/llvm/test/TableGen/intrinsic-varargs.td
+++ b/llvm/test/TableGen/intrinsic-varargs.td
@@ -3,5 +3,5 @@
include "llvm/IR/Intrinsics.td"
-// CHECK: /* 0 */ 0, 30, 0,
+// CHECK: /* 0 */ 0, 29, 0,
def int_foo : Intrinsic<[], [llvm_vararg_ty]>;
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