[llvm] [RISCV] Add codegen support for Zvfbfmin (PR #87911)

[Craig Topper via llvm-commits]

================
@@ -301,3 +301,21 @@ define void @v2i8_volatile_store(ptr %p, ptr %q) {
   store volatile <2 x i8> %v, ptr %q
   ret void
 }
+
+define void @v4bf16(ptr %p, ptr %q) {
+; RV32-LABEL: v4bf16:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; RV32-NEXT:    vle16.v v8, (a0)
+; RV32-NEXT:    vse16.v v8, (a1)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: v4bf16:
+; RV64:       # %bb.0:
+; RV64-NEXT:    ld a0, 0(a0)
----------------
topperc wrote:

Please use a type that doesn't convert to i64 on RV64

https://github.com/llvm/llvm-project/pull/87911