[llvm] [RISCV] Add codegen support for Zvfbfmin (PR #87911)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 9 15:06:20 PDT 2024
================
@@ -1080,6 +1080,21 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
}
+ // TODO: Could we merge some code with zvfhmin?
+ if (Subtarget.hasVInstructionsBF16()) {
+ for (MVT VT : BF16VecVTs) {
+ if (!isTypeLegal(VT))
+ continue;
+ setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
+ setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
+ setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
+ ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR},
+ VT, Custom);
+ setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
+ // TODO: Promote to fp32.
----------------
topperc wrote:
Zvfbfmin does not have any integer conversion instructions so `SINT_TO_FP, UINT_TO_FP, VP_SINT_TO_FP, VP_UINT_TO_FP` can be removed.
https://github.com/llvm/llvm-project/pull/87911
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