[llvm] [AArch64] Improve scheduling latency into Bundles (PR #86310)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 9 08:35:48 PDT 2024
================
@@ -472,6 +472,45 @@ void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
}
+void AArch64Subtarget::adjustSchedDependency(
+ SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep,
+ const TargetSchedModel *SchedModel) const {
+ if (!SchedModel || Dep.getKind() != SDep::Kind::Data || !Dep.getReg() ||
+ !Def->isInstr() || !Use->isInstr() ||
+ (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE &&
+ Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE))
+ return;
+
+ // If the Def is a BUNDLE, find the last instruction in the bundle that defs
+ // the register.
+ const MachineInstr *DefMI = Def->getInstr();
+ if (DefMI->getOpcode() == TargetOpcode::BUNDLE) {
+ Register Reg = DefMI->getOperand(DefOpIdx).getReg();
----------------
davemgreen wrote:
On the Bundle? Yep I believe they will always be registers, especially the DefOpIdx. It checks above that the dependency is a Reg.
https://github.com/llvm/llvm-project/pull/86310
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