[llvm] [AArch64] Combine getActiveLaneMask with vector_extract (PR #81139)

[David Sherwood via llvm-commits]

================
@@ -20507,6 +20507,61 @@ static SDValue convertMergedOpToPredOp(SDNode *N, unsigned Opc,
   return SDValue();
 }
 
+static SDValue tryCombineWhileLo(SDNode *N,
+                                 TargetLowering::DAGCombinerInfo &DCI,
+                                 const AArch64Subtarget *Subtarget) {
+  if (DCI.isBeforeLegalize())
+    return SDValue();
+
+  if (!Subtarget->hasSVE2p1() && !Subtarget->hasSME2())
+    return SDValue();
+
+  if (!N->hasNUsesOfValue(2, 0))
+    return SDValue();
+
+  const uint64_t HalfSize = N->getValueType(0).getVectorMinNumElements() / 2;
+  if (HalfSize < 2)
+    return SDValue();
+
+  auto It = N->use_begin();
+  SDNode *Lo = *It++;
+  SDNode *Hi = *It;
+
+  uint64_t OffLo, OffHi;
+  if (Lo->getOpcode() != ISD::EXTRACT_SUBVECTOR ||
----------------
david-arm wrote:

>From reading the definition of the opcode EXTRACT_SUBVECTOR I see:

```
  /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
  /// Let the result type be T, then IDX represents the starting element number
  /// from which a subvector of type T is extracted. IDX must be a constant
  /// multiple of T's known minimum vector length.
```

so since the IDX must be a constant I think you can just do something like:

```
  if (Lo->getOpcode() != ISD::EXTRACT_SUBVECTOR ||
      Hi->getOpcode() != ISD::EXTRACT_SUBVECTOR)
    return SDValue();
  uint64_t OffLo = Lo->getConstantOperandVal(1);
  uint64_t OffHi = Hi->getConstantOperandVal(1);
```

https://github.com/llvm/llvm-project/pull/81139