[llvm] fb8dbd1 - [AArch64] Remove copy in SVE/SME predicate spill and fill (#81716)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 9 08:17:32 PDT 2024
Author: Sam Tebbs
Date: 2024-04-09T16:17:27+01:00
New Revision: fb8dbd1fb67ef4d1417f279df7f9a99b29468527
URL: https://github.com/llvm/llvm-project/commit/fb8dbd1fb67ef4d1417f279df7f9a99b29468527
DIFF: https://github.com/llvm/llvm-project/commit/fb8dbd1fb67ef4d1417f279df7f9a99b29468527.diff
LOG: [AArch64] Remove copy in SVE/SME predicate spill and fill (#81716)
7dc20ab introduced an extra COPY when spilling and filling a PNR
register, which can't be elided as the input (PNR predicate) and output
(PPR predicate) register classes differ. The patch adds a new register
class that covers both PPR and PNR so that STR_PXI and LDR_PXI can
take either of them, removing the need for the copy.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/SMEInstrFormats.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
llvm/test/CodeGen/AArch64/spillfill-sve.mir
llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 22687b0e31c284..9783b33219460c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4807,29 +4807,20 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::STRBui;
break;
- case 2:
+ case 2: {
+ bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
Opc = AArch64::STRHui;
- else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
+ else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasSVEorSME() &&
"Unexpected register store without SVE store instructions");
- Opc = AArch64::STR_PXI;
- StackID = TargetStackID::ScalableVector;
- } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
- assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
+ assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
"Unexpected register store without SVE2p1 or SME2");
- if (SrcReg.isVirtual()) {
- auto NewSrcReg =
- MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
- BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg)
- .addReg(SrcReg);
- SrcReg = NewSrcReg;
- } else
- SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
Opc = AArch64::STR_PXI;
StackID = TargetStackID::ScalableVector;
}
break;
+ }
case 4:
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::STRWui;
@@ -4990,26 +4981,22 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRBui;
break;
- case 2:
+ case 2: {
+ bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRHui;
- else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
+ else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasSVEorSME() &&
"Unexpected register load without SVE load instructions");
- Opc = AArch64::LDR_PXI;
- StackID = TargetStackID::ScalableVector;
- } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
- assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
+ assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
"Unexpected register load without SVE2p1 or SME2");
- PNRReg = DestReg;
- if (DestReg.isVirtual())
- DestReg = MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
- else
- DestReg = (DestReg - AArch64::PN0) + AArch64::P0;
+ if (IsPNR)
+ PNRReg = DestReg;
Opc = AArch64::LDR_PXI;
StackID = TargetStackID::ScalableVector;
}
break;
+ }
case 4:
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::LDRWui;
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index fef1748021b07c..80d0f9c57f4b36 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -953,17 +953,6 @@ class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
}
-let RenderMethod = "addPNRasPPRRegOperands" in {
- def PNRasPPROpAny : PNRAsmOperand<"PNRasPPRPredicateAny", "PNR", 0>;
- def PNRasPPROp8 : PNRAsmOperand<"PNRasPPRPredicateB", "PNR", 8>;
-}
-
-class PNRasPPRRegOp<string Suffix, AsmOperandClass C, ElementSizeEnum Size,
- RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
-
-def PNRasPPRAny : PNRasPPRRegOp<"", PNRasPPROpAny, ElementSizeNone, PPR>;
-def PNRasPPR8 : PNRasPPRRegOp<"b", PNRasPPROp8, ElementSizeB, PPR>;
-
def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>;
def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>;
def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>;
@@ -1004,6 +993,29 @@ let Namespace = "AArch64" in {
def psub1 : SubRegIndex<16, -1>;
}
+class PPRorPNRClass : RegisterClass<
+ "AArch64",
+ [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16,
+ (add PPR, PNR)> {
+ let Size = 16;
+}
+
+class PPRorPNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
+ let Name = "SVE" # name # "Reg";
+ let PredicateMethod = "isSVEPredicateOrPredicateAsCounterRegOfWidth<"
+ # Width # ", " # "AArch64::"
+ # RegClass # "RegClassID>";
+ let DiagnosticType = "InvalidSVE" # name # "Reg";
+ let RenderMethod = "addPPRorPNRRegOperands";
+ let ParserMethod = "tryParseSVEPredicateOrPredicateAsCounterVector";
+}
+
+def PPRorPNR : PPRorPNRClass;
+def PPRorPNRAsmOp8 : PPRorPNRAsmOperand<"PPRorPNRB", "PPRorPNR", 8>;
+def PPRorPNRAsmOpAny : PPRorPNRAsmOperand<"PPRorPNRAny", "PPRorPNR", 0>;
+def PPRorPNRAny : PPRRegOp<"", PPRorPNRAsmOpAny, ElementSizeNone, PPRorPNR>;
+def PPRorPNR8 : PPRRegOp<"b", PPRorPNRAsmOp8, ElementSizeB, PPRorPNR>;
+
// Pairs of SVE predicate vector registers.
def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index a519d81362a73a..9c747198c12d86 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -4034,20 +4034,10 @@ let Predicates = [HasSVEorSME] in {
// Aliases for existing SVE instructions for which predicate-as-counter are
// accepted as an operand to the instruction
-def : InstAlias<"ldr $Pt, [$Rn, $imm9, mul vl]",
- (LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
-def : InstAlias<"ldr $Pt, [$Rn]",
- (LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;
-
-def : InstAlias<"str $Pt, [$Rn, $imm9, mul vl]",
- (STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
-def : InstAlias<"str $Pt, [$Rn]",
- (STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;
-
def : InstAlias<"mov $Pd, $Pn",
- (ORR_PPzPP PNRasPPR8:$Pd, PNRasPPR8:$Pn, PNRasPPR8:$Pn, PNRasPPR8:$Pn), 0>;
+ (ORR_PPzPP PPRorPNR8:$Pd, PPRorPNR8:$Pn, PPRorPNR8:$Pn, PPRorPNR8:$Pn), 0>;
-def : InstAlias<"pfalse\t$Pd", (PFALSE PNRasPPR8:$Pd), 0>;
+def : InstAlias<"pfalse\t$Pd", (PFALSE PPRorPNR8:$Pd), 0>;
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 21643ebb413847..a3b966aa61550c 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -276,6 +276,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
ParseStatus tryParseSVEDataVector(OperandVector &Operands);
template <RegKind RK>
ParseStatus tryParseSVEPredicateVector(OperandVector &Operands);
+ ParseStatus
+ tryParseSVEPredicateOrPredicateAsCounterVector(OperandVector &Operands);
template <RegKind VectorKind>
ParseStatus tryParseVectorList(OperandVector &Operands,
bool ExpectMatch = false);
@@ -1241,6 +1243,7 @@ class AArch64Operand : public MCParsedAsmOperand {
case AArch64::PPR_p8to15RegClassID:
case AArch64::PNRRegClassID:
case AArch64::PNR_p8to15RegClassID:
+ case AArch64::PPRorPNRRegClassID:
RK = RegKind::SVEPredicateAsCounter;
break;
default:
@@ -1264,6 +1267,7 @@ class AArch64Operand : public MCParsedAsmOperand {
case AArch64::PPR_p8to15RegClassID:
case AArch64::PNRRegClassID:
case AArch64::PNR_p8to15RegClassID:
+ case AArch64::PPRorPNRRegClassID:
RK = RegKind::SVEPredicateVector;
break;
default:
@@ -1290,6 +1294,20 @@ class AArch64Operand : public MCParsedAsmOperand {
return DiagnosticPredicateTy::NearMatch;
}
+ template <int ElementWidth, unsigned Class>
+ DiagnosticPredicate isSVEPredicateOrPredicateAsCounterRegOfWidth() const {
+ if (Kind != k_Register || (Reg.Kind != RegKind::SVEPredicateAsCounter &&
+ Reg.Kind != RegKind::SVEPredicateVector))
+ return DiagnosticPredicateTy::NoMatch;
+
+ if ((isSVEPredicateAsCounterReg<Class>() ||
+ isSVEPredicateVectorRegOfWidth<ElementWidth, Class>()) &&
+ Reg.ElementWidth == ElementWidth)
+ return DiagnosticPredicateTy::Match;
+
+ return DiagnosticPredicateTy::NearMatch;
+ }
+
template <int ElementWidth, unsigned Class>
DiagnosticPredicate isSVEPredicateAsCounterRegOfWidth() const {
if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateAsCounter)
@@ -1770,6 +1788,15 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
}
+ void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ unsigned Reg = getReg();
+ // Normalise to PPR
+ if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15)
+ Reg = Reg - AArch64::PN0 + AArch64::P0;
+ Inst.addOperand(MCOperand::createReg(Reg));
+ }
+
void addPNRasPPRRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(
@@ -4167,6 +4194,15 @@ ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg,
return ParseStatus::NoMatch;
}
+ParseStatus AArch64AsmParser::tryParseSVEPredicateOrPredicateAsCounterVector(
+ OperandVector &Operands) {
+ ParseStatus Status =
+ tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>(Operands);
+ if (!Status.isSuccess())
+ Status = tryParseSVEPredicateVector<RegKind::SVEPredicateVector>(Operands);
+ return Status;
+}
+
/// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
template <RegKind RK>
ParseStatus
@@ -6019,6 +6055,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
return Error(Loc, "Invalid restricted vector register, expected z0.d..z15.d");
case Match_InvalidSVEPattern:
return Error(Loc, "invalid predicate pattern");
+ case Match_InvalidSVEPPRorPNRAnyReg:
+ case Match_InvalidSVEPPRorPNRBReg:
case Match_InvalidSVEPredicateAnyReg:
case Match_InvalidSVEPredicateBReg:
case Match_InvalidSVEPredicateHReg:
@@ -6131,9 +6169,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
case Match_AddSubLSLImm3ShiftLarge:
return Error(Loc,
"expected 'lsl' with optional integer in range [0, 7]");
- case Match_InvalidSVEPNRasPPRPredicateBReg:
- return Error(Loc,
- "Expected predicate-as-counter register name with .B suffix");
default:
llvm_unreachable("unexpected error code!");
}
@@ -6653,6 +6688,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidZPR_4b16:
case Match_InvalidZPR_4b32:
case Match_InvalidZPR_4b64:
+ case Match_InvalidSVEPPRorPNRAnyReg:
+ case Match_InvalidSVEPPRorPNRBReg:
case Match_InvalidSVEPredicateAnyReg:
case Match_InvalidSVEPattern:
case Match_InvalidSVEVecLenSpecifier:
@@ -6714,7 +6751,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSVEVectorListStrided4x16:
case Match_InvalidSVEVectorListStrided4x32:
case Match_InvalidSVEVectorListStrided4x64:
- case Match_InvalidSVEPNRasPPRPredicateBReg:
case Match_MSR:
case Match_MRS: {
if (ErrorInfo >= Operands.size())
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index a21b4b77166ede..ddb875e73ff5a9 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -143,6 +143,9 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
+static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Addr,
+ const MCDisassembler *Decoder);
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
@@ -741,6 +744,18 @@ static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
return Success;
}
+static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t Addr,
+ const MCDisassembler *Decoder) {
+ if (RegNo > 15)
+ return Fail;
+
+ unsigned Register =
+ AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo);
+ Inst.addOperand(MCOperand::createReg(Register));
+ return Success;
+}
+
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr,
const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 44d9a8ac7cb677..3363aab4b093cc 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1301,7 +1301,7 @@ multiclass sve2_clamp<string asm, bit U, SDPatternOperator op> {
}
class sve2_int_perm_sel_p<string asm, PPRRegOp ppr_ty, Operand imm_ty>
- : I<(outs PPRAny:$Pd), (ins PPRAny:$Pn, ppr_ty:$Pm,
+ : I<(outs PPRorPNRAny:$Pd), (ins PPRorPNRAny:$Pn, ppr_ty:$Pm,
MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>,
Sched<[]> {
@@ -1345,19 +1345,6 @@ multiclass sve2_int_perm_sel_p<string asm, SDPatternOperator op> {
let Inst{20-18} = 0b000;
}
- def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
- (!cast<Instruction>(NAME # _B) PNRasPPRAny:$Pd,
- PNRasPPRAny:$Pn, PPR8:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm), 0>;
- def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
- (!cast<Instruction>(NAME # _H) PNRasPPRAny:$Pd,
- PNRasPPRAny:$Pn, PPR16:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm), 0>;
- def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
- (!cast<Instruction>(NAME # _S) PNRasPPRAny:$Pd,
- PNRasPPRAny:$Pn, PPR32:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm), 0>;
- def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
- (!cast<Instruction>(NAME # _D) PNRasPPRAny:$Pd,
- PNRasPPRAny:$Pn, PPR64:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm), 0>;
-
def : Pat<(nxv16i1 (op (nxv16i1 PPRAny:$Pn), (nxv16i1 PPR8:$Pm),
MatrixIndexGPR32Op12_15:$idx)),
(!cast<Instruction>(NAME # _B) $Pn, $Pm, $idx, 0)>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index ee8292fdd8839a..fb0c6188edb348 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -729,7 +729,7 @@ let hasNoSchedulingInfo = 1 in {
//===----------------------------------------------------------------------===//
class sve_int_pfalse<bits<6> opc, string asm>
-: I<(outs PPR8:$Pd), (ins),
+: I<(outs PPRorPNR8:$Pd), (ins),
asm, "\t$Pd",
"",
[]>, Sched<[]> {
@@ -1837,7 +1837,7 @@ multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> {
//===----------------------------------------------------------------------===//
class sve_int_pred_log<bits<4> opc, string asm>
-: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
+: I<(outs PPRorPNR8:$Pd), (ins PPRorPNRAny:$Pg, PPRorPNR8:$Pn, PPRorPNR8:$Pm),
asm, "\t$Pd, $Pg/z, $Pn, $Pm",
"",
[]>, Sched<[]> {
@@ -6664,7 +6664,7 @@ multiclass sve_mem_z_spill<string asm> {
}
class sve_mem_p_spill<string asm>
-: I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
+: I<(outs), (ins PPRorPNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
asm, "\t$Pt, [$Rn, $imm9, mul vl]",
"",
[]>, Sched<[]> {
@@ -6687,7 +6687,7 @@ multiclass sve_mem_p_spill<string asm> {
def NAME : sve_mem_p_spill<asm>;
def : InstAlias<asm # "\t$Pt, [$Rn]",
- (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
+ (!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>;
}
//===----------------------------------------------------------------------===//
@@ -7833,7 +7833,7 @@ multiclass sve_mem_z_fill<string asm> {
}
class sve_mem_p_fill<string asm>
-: I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
+: I<(outs PPRorPNRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
asm, "\t$Pt, [$Rn, $imm9, mul vl]",
"",
[]>, Sched<[]> {
@@ -7856,7 +7856,7 @@ multiclass sve_mem_p_fill<string asm> {
def NAME : sve_mem_p_fill<asm>;
def : InstAlias<asm # "\t$Pt, [$Rn]",
- (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
+ (!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>;
}
class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
index e77fac19e0a78a..2ffb7856806850 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
@@ -57,11 +57,11 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_reg_output
- ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0
+ ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common
+ INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common
%1:_(s32) = COPY %0
$w0 = COPY %1(s32)
RET_ReallyLR implicit $w0
@@ -75,12 +75,12 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_mixed_types
- ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0, 2162698 /* regdef:WSeqPairsClass */, def %1
+ ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common, 2162698 /* regdef:FPR64 */, def %1:fpr64
+ INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common, 2621450 /* regdef:FPR64 */, def %1:fpr64
%3:_(s32) = COPY %0
%4:_(s64) = COPY %1
$d0 = COPY %4(s64)
diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
index 92fb053b0db726..2be7aba2a3df89 100644
--- a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
+++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
@@ -91,10 +91,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
@@ -111,10 +111,10 @@ body: |
%6:gpr64common = LOADgot target-flags(aarch64-got) @c
%3:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
- INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
%0:fpr64 = COPY %2
%5:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
- INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
%7:fpr64 = FNEGDr %2
nofpexcept FCMPDrr %4, killed %7, implicit-def $nzcv, implicit $fpcr
Bcc 1, %bb.2, implicit $nzcv
diff --git a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
index 65148344096cd7..5dd29cf39c0ead 100644
--- a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
@@ -487,7 +487,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
- ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2621450 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
@@ -505,7 +505,7 @@ body: |
%0:gpr64common = COPY $x0
%2:gpr64all = IMPLICIT_DEF
%3:gpr64sp = COPY %2
- INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
+ INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2621450 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
%4:fpr128 = MOVIv2d_ns 0
%5:fpr64 = COPY %4.dsub
%7:fpr128 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/spillfill-sve.mir b/llvm/test/CodeGen/AArch64/spillfill-sve.mir
index ef7d55a1c2395f..11cf388e385312 100644
--- a/llvm/test/CodeGen/AArch64/spillfill-sve.mir
+++ b/llvm/test/CodeGen/AArch64/spillfill-sve.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=greedy %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-linux-gnu -start-before=greedy -stop-after=aarch64-expand-pseudo %s -o - | FileCheck %s --check-prefix=EXPAND
+# RUN: llc -mtriple=aarch64-linux-gnu -start-before=greedy -stop-after=aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=EXPAND
--- |
; ModuleID = '<stdin>'
source_filename = "<stdin>"
@@ -173,8 +173,8 @@ body: |
; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: ''
; EXPAND-LABEL: name: spills_fills_stack_id_pnr
- ; EXPAND: STR_PXI $p0, $sp, 7
- ; EXPAND: $p0 = LDR_PXI $sp, 7, implicit-def $pn0
+ ; EXPAND: STR_PXI $pn0, $sp, 7
+ ; EXPAND: $pn0 = LDR_PXI $sp, 7, implicit-def $pn0
%0:pnr = COPY $pn0
@@ -213,11 +213,9 @@ body: |
; EXPAND-LABEL: name: spills_fills_stack_id_virtreg_pnr
; EXPAND: renamable $pn8 = WHILEGE_CXX_B
- ; EXPAND: $p0 = ORR_PPzPP $p8, $p8, killed $p8
- ; EXPAND: STR_PXI killed renamable $p0, $sp, 7
+ ; EXPAND: STR_PXI killed renamable $pn8, $sp, 7
;
- ; EXPAND: renamable $p0 = LDR_PXI $sp, 7
- ; EXPAND: $p8 = ORR_PPzPP $p0, $p0, killed $p0, implicit-def $pn8
+ ; EXPAND: renamable $pn8 = LDR_PXI $sp, 7
; EXPAND: $p0 = PEXT_PCI_B killed renamable $pn8, 0
diff --git a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
index f4d95c5910d895..e44453b4c3265d 100644
--- a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
@@ -17,6 +17,6 @@ pfalse pn16.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pfalse pn5.d
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Expected predicate-as-counter register name with .B suffix
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: pfalse pn5.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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