[llvm] Fix to Neoverse V2 scheduling model (PR #88130)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Maciej Gabka (mgabka)

<details>
<summary>Changes</summary>

The size of ROB was incorrecty copied from the Neoverse N2, while it has actually higher value as descibed in
https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/arm-neoverse-v2-platform-best-in-class-cloud-and-ai-ml-performance

---
Full diff: https://github.com/llvm/llvm-project/pull/88130.diff


1 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 4d7f44e7b9b9ab..7fed8fed900171 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -15,7 +15,7 @@
 
 def NeoverseV2Model : SchedMachineModel {
   let IssueWidth            =  16; // Micro-ops dispatched at a time.
-  let MicroOpBufferSize     = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2.
+  let MicroOpBufferSize     = 320; // Entries in micro-op re-order buffer.
   let LoadLatency           =   4; // Optimistic load latency.
   let MispredictPenalty     =  10; // Extra cycles for mispredicted branch.  NOTE: Copied from N2.
   let LoopMicroOpBufferSize =  16; // NOTE: Copied from Cortex-A57.

``````````

</details>


https://github.com/llvm/llvm-project/pull/88130