[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Craig Topper via llvm-commits]

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@@ -950,10 +1074,12 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
   }
 
   if (Info.hasAVLImm()) {
-    BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
-        .addReg(RISCV::X0, RegState::Define | RegState::Dead)
-        .addImm(Info.getAVLImm())
-        .addImm(Info.encodeVTYPE());
+    auto NeedFixupMI =
+        BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
+            .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+            .addImm(Info.getAVLImm())
+            .addImm(Info.encodeVTYPE());
+    fixupModifyVRegLIAfterInsertMI(NeedFixupMI, LIS);
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topperc wrote:

The instruction just inserted writes X0 and doesn't read any register. Do we need any fixup?

https://github.com/llvm/llvm-project/pull/70549