[llvm] [MachineCombiner][NFC] Split target-dependent patterns (PR #87991)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 8 20:42:06 PDT 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/87991
>From 889ffbd28b8e40e2e6d5f6132c942d6db546806e Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Mon, 8 Apr 2024 21:40:08 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.6-beta.1
---
.../llvm/CodeGen/MachineCombinerPattern.h | 166 +----
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 25 +-
llvm/lib/CodeGen/MachineCombiner.cpp | 72 +--
llvm/lib/CodeGen/TargetInstrInfo.cpp | 20 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 574 +++++++++---------
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 152 ++++-
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 83 +--
llvm/lib/Target/PowerPC/PPCInstrInfo.h | 26 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 72 ++-
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 21 +-
llvm/lib/Target/X86/X86InstrInfo.cpp | 17 +-
llvm/lib/Target/X86/X86InstrInfo.h | 15 +-
12 files changed, 635 insertions(+), 608 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
index 89eed7463bd783..ed87667662663a 100644
--- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -16,8 +16,16 @@
namespace llvm {
+/// The combiner's goal may differ based on which pattern it is attempting
+/// to optimize.
+enum class CombinerObjective {
+ MustReduceDepth, // The data dependency chain must be improved.
+ MustReduceRegisterPressure, // The register pressure must be reduced.
+ Default // The critical path must not be lengthened.
+};
+
/// These are instruction patterns matched by the machine combiner pass.
-enum class MachineCombinerPattern {
+enum MachineCombinerPattern {
// These are commutative variants for reassociating a computation chain. See
// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
REASSOC_AX_BY,
@@ -25,161 +33,7 @@ enum class MachineCombinerPattern {
REASSOC_XA_BY,
REASSOC_XA_YB,
- // These are patterns matched by the PowerPC to reassociate FMA chains.
- REASSOC_XY_AMM_BMM,
- REASSOC_XMM_AMM_BMM,
-
- // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
- // reduce register pressure.
- REASSOC_XY_BCA,
- REASSOC_XY_BAC,
-
- // These are patterns used to reduce the length of dependence chain.
- SUBADD_OP1,
- SUBADD_OP2,
-
- // These are multiply-add patterns matched by the AArch64 machine combiner.
- MULADDW_OP1,
- MULADDW_OP2,
- MULSUBW_OP1,
- MULSUBW_OP2,
- MULADDWI_OP1,
- MULSUBWI_OP1,
- MULADDX_OP1,
- MULADDX_OP2,
- MULSUBX_OP1,
- MULSUBX_OP2,
- MULADDXI_OP1,
- MULSUBXI_OP1,
- // NEON integers vectors
- MULADDv8i8_OP1,
- MULADDv8i8_OP2,
- MULADDv16i8_OP1,
- MULADDv16i8_OP2,
- MULADDv4i16_OP1,
- MULADDv4i16_OP2,
- MULADDv8i16_OP1,
- MULADDv8i16_OP2,
- MULADDv2i32_OP1,
- MULADDv2i32_OP2,
- MULADDv4i32_OP1,
- MULADDv4i32_OP2,
-
- MULSUBv8i8_OP1,
- MULSUBv8i8_OP2,
- MULSUBv16i8_OP1,
- MULSUBv16i8_OP2,
- MULSUBv4i16_OP1,
- MULSUBv4i16_OP2,
- MULSUBv8i16_OP1,
- MULSUBv8i16_OP2,
- MULSUBv2i32_OP1,
- MULSUBv2i32_OP2,
- MULSUBv4i32_OP1,
- MULSUBv4i32_OP2,
-
- MULADDv4i16_indexed_OP1,
- MULADDv4i16_indexed_OP2,
- MULADDv8i16_indexed_OP1,
- MULADDv8i16_indexed_OP2,
- MULADDv2i32_indexed_OP1,
- MULADDv2i32_indexed_OP2,
- MULADDv4i32_indexed_OP1,
- MULADDv4i32_indexed_OP2,
-
- MULSUBv4i16_indexed_OP1,
- MULSUBv4i16_indexed_OP2,
- MULSUBv8i16_indexed_OP1,
- MULSUBv8i16_indexed_OP2,
- MULSUBv2i32_indexed_OP1,
- MULSUBv2i32_indexed_OP2,
- MULSUBv4i32_indexed_OP1,
- MULSUBv4i32_indexed_OP2,
-
- // Floating Point
- FMULADDH_OP1,
- FMULADDH_OP2,
- FMULSUBH_OP1,
- FMULSUBH_OP2,
- FMULADDS_OP1,
- FMULADDS_OP2,
- FMULSUBS_OP1,
- FMULSUBS_OP2,
- FMULADDD_OP1,
- FMULADDD_OP2,
- FMULSUBD_OP1,
- FMULSUBD_OP2,
- FNMULSUBH_OP1,
- FNMULSUBS_OP1,
- FNMULSUBD_OP1,
- FMLAv1i32_indexed_OP1,
- FMLAv1i32_indexed_OP2,
- FMLAv1i64_indexed_OP1,
- FMLAv1i64_indexed_OP2,
- FMLAv4f16_OP1,
- FMLAv4f16_OP2,
- FMLAv8f16_OP1,
- FMLAv8f16_OP2,
- FMLAv2f32_OP2,
- FMLAv2f32_OP1,
- FMLAv2f64_OP1,
- FMLAv2f64_OP2,
- FMLAv4i16_indexed_OP1,
- FMLAv4i16_indexed_OP2,
- FMLAv8i16_indexed_OP1,
- FMLAv8i16_indexed_OP2,
- FMLAv2i32_indexed_OP1,
- FMLAv2i32_indexed_OP2,
- FMLAv2i64_indexed_OP1,
- FMLAv2i64_indexed_OP2,
- FMLAv4f32_OP1,
- FMLAv4f32_OP2,
- FMLAv4i32_indexed_OP1,
- FMLAv4i32_indexed_OP2,
- FMLSv1i32_indexed_OP2,
- FMLSv1i64_indexed_OP2,
- FMLSv4f16_OP1,
- FMLSv4f16_OP2,
- FMLSv8f16_OP1,
- FMLSv8f16_OP2,
- FMLSv2f32_OP1,
- FMLSv2f32_OP2,
- FMLSv2f64_OP1,
- FMLSv2f64_OP2,
- FMLSv4i16_indexed_OP1,
- FMLSv4i16_indexed_OP2,
- FMLSv8i16_indexed_OP1,
- FMLSv8i16_indexed_OP2,
- FMLSv2i32_indexed_OP1,
- FMLSv2i32_indexed_OP2,
- FMLSv2i64_indexed_OP1,
- FMLSv2i64_indexed_OP2,
- FMLSv4f32_OP1,
- FMLSv4f32_OP2,
- FMLSv4i32_indexed_OP1,
- FMLSv4i32_indexed_OP2,
-
- FMULv2i32_indexed_OP1,
- FMULv2i32_indexed_OP2,
- FMULv2i64_indexed_OP1,
- FMULv2i64_indexed_OP2,
- FMULv4i16_indexed_OP1,
- FMULv4i16_indexed_OP2,
- FMULv4i32_indexed_OP1,
- FMULv4i32_indexed_OP2,
- FMULv8i16_indexed_OP1,
- FMULv8i16_indexed_OP2,
-
- // RISCV FMADD, FMSUB, FNMSUB patterns
- FMADD_AX,
- FMADD_XA,
- FMSUB,
- FNMSUB,
-
- // X86 VNNI
- DPWSSD,
-
- FNMADD,
+ TARGET_PATTERN_START
};
} // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 9fd0ebe6956fbe..658092e192dd33 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -19,6 +19,7 @@
#include "llvm/ADT/Uniformity.h"
#include "llvm/CodeGen/MIRFormatter.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineCycleAnalysis.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -61,7 +62,6 @@ class TargetRegisterClass;
class TargetRegisterInfo;
class TargetSchedModel;
class TargetSubtargetInfo;
-enum class MachineCombinerPattern;
enum class MachineTraceStrategy;
template <class T> class SmallVectorImpl;
@@ -1191,10 +1191,9 @@ class TargetInstrInfo : public MCInstrInfo {
/// faster sequence.
/// \param Root - Instruction that could be combined with one of its operands
/// \param Patterns - Vector of possible combination patterns
- virtual bool
- getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const;
+ virtual bool getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const;
/// Return true if target supports reassociation of instructions in machine
/// combiner pass to reduce register pressure for a given BB.
@@ -1206,13 +1205,17 @@ class TargetInstrInfo : public MCInstrInfo {
/// Fix up the placeholder we may add in genAlternativeCodeSequence().
virtual void
- finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
+ finalizeInsInstrs(MachineInstr &Root, int &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
- virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
+ virtual bool isThroughputPattern(int Pattern) const;
+
+ /// Return the objective of a combiner pattern.
+ /// \param Pattern - combiner pattern
+ virtual CombinerObjective getCombinerObjective(int Pattern) const;
/// Return true if the input \P Inst is part of a chain of dependent ops
/// that are suitable for reassociation, otherwise return false.
@@ -1256,7 +1259,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// \param InstIdxForVirtReg - map of virtual register to instruction in
/// InsInstr that defines it
virtual void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
+ MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
@@ -1270,8 +1273,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
/// reduce critical path length.
- void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
+ void reassociateOps(MachineInstr &Root, MachineInstr &Prev, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
@@ -1281,8 +1283,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// (new root opcode, new prev opcode) that must be used to reassociate \P
/// Root and \P Prev accoring to \P Pattern.
std::pair<unsigned, unsigned>
- getReassociationOpcodes(MachineCombinerPattern Pattern,
- const MachineInstr &Root,
+ getReassociationOpcodes(int Pattern, const MachineInstr &Root,
const MachineInstr &Prev) const;
/// The limit on resource length extension we accept in MachineCombiner Pass.
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index a4c87a7678bd8d..f30323611ca837 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -99,17 +99,16 @@ class MachineCombiner : public MachineFunctionPass {
const MachineBasicBlock &MBB);
unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
MachineTraceMetrics::Trace BlockTrace);
- bool
- improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
- MachineTraceMetrics::Trace BlockTrace,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
- MachineCombinerPattern Pattern, bool SlackIsAccurate);
+ bool improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
+ MachineTraceMetrics::Trace BlockTrace,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
+ int Pattern, bool SlackIsAccurate);
bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineCombinerPattern Pattern);
+ int Pattern);
bool preservesResourceLen(MachineBasicBlock *MBB,
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -123,7 +122,8 @@ class MachineCombiner : public MachineFunctionPass {
MachineTraceMetrics::Trace BlockTrace);
void verifyPatternOrder(MachineBasicBlock *MBB, MachineInstr &Root,
- SmallVector<MachineCombinerPattern, 16> &Patterns);
+ SmallVector<int, 16> &Patterns);
+ CombinerObjective getCombinerObjective(int Pattern);
};
}
@@ -290,36 +290,17 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
return NewRootLatency;
}
-/// The combiner's goal may differ based on which pattern it is attempting
-/// to optimize.
-enum class CombinerObjective {
- MustReduceDepth, // The data dependency chain must be improved.
- MustReduceRegisterPressure, // The register pressure must be reduced.
- Default // The critical path must not be lengthened.
-};
-
-static CombinerObjective getCombinerObjective(MachineCombinerPattern P) {
+CombinerObjective MachineCombiner::getCombinerObjective(int Pattern) {
// TODO: If C++ ever gets a real enum class, make this part of the
// MachineCombinerPattern class.
- switch (P) {
+ switch (Pattern) {
case MachineCombinerPattern::REASSOC_AX_BY:
case MachineCombinerPattern::REASSOC_AX_YB:
case MachineCombinerPattern::REASSOC_XA_BY:
case MachineCombinerPattern::REASSOC_XA_YB:
- case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
- case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
- case MachineCombinerPattern::SUBADD_OP1:
- case MachineCombinerPattern::SUBADD_OP2:
- case MachineCombinerPattern::FMADD_AX:
- case MachineCombinerPattern::FMADD_XA:
- case MachineCombinerPattern::FMSUB:
- case MachineCombinerPattern::FNMSUB:
return CombinerObjective::MustReduceDepth;
- case MachineCombinerPattern::REASSOC_XY_BCA:
- case MachineCombinerPattern::REASSOC_XY_BAC:
- return CombinerObjective::MustReduceRegisterPressure;
default:
- return CombinerObjective::Default;
+ return TII->getCombinerObjective(Pattern);
}
}
@@ -349,8 +330,7 @@ std::pair<unsigned, unsigned> MachineCombiner::getLatenciesForInstrSequences(
bool MachineCombiner::reduceRegisterPressure(
MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineCombinerPattern Pattern) {
+ SmallVectorImpl<MachineInstr *> &DelInstrs, int Pattern) {
// FIXME: for now, we don't do any check for the register pressure patterns.
// We treat them as always profitable. But we can do better if we make
// RegPressureTracker class be aware of TIE attribute. Then we can get an
@@ -368,8 +348,7 @@ bool MachineCombiner::improvesCriticalPathLen(
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
- MachineCombinerPattern Pattern,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, int Pattern,
bool SlackIsAccurate) {
// Get depth and latency of NewRoot and Root.
unsigned NewRootDepth =
@@ -493,13 +472,14 @@ bool MachineCombiner::preservesResourceLen(
/// \param Pattern is used to call target hook finalizeInsInstrs
/// \param IncrementalUpdate if true, compute instruction depths incrementally,
/// otherwise invalidate the trace
-static void insertDeleteInstructions(
- MachineBasicBlock *MBB, MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs,
- MachineTraceMetrics::Ensemble *TraceEnsemble,
- SparseSet<LiveRegUnit> &RegUnits, const TargetInstrInfo *TII,
- MachineCombinerPattern Pattern, bool IncrementalUpdate) {
+static void
+insertDeleteInstructions(MachineBasicBlock *MBB, MachineInstr &MI,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
+ SmallVectorImpl<MachineInstr *> &DelInstrs,
+ MachineTraceMetrics::Ensemble *TraceEnsemble,
+ SparseSet<LiveRegUnit> &RegUnits,
+ const TargetInstrInfo *TII, int Pattern,
+ bool IncrementalUpdate) {
// If we want to fix up some placeholder for some target, do it now.
// We need this because in genAlternativeCodeSequence, we have not decided the
// better pattern InsInstrs or DelInstrs, so we don't want generate some
@@ -534,9 +514,9 @@ static void insertDeleteInstructions(
// Check that the difference between original and new latency is decreasing for
// later patterns. This helps to discover sub-optimal pattern orderings.
-void MachineCombiner::verifyPatternOrder(
- MachineBasicBlock *MBB, MachineInstr &Root,
- SmallVector<MachineCombinerPattern, 16> &Patterns) {
+void MachineCombiner::verifyPatternOrder(MachineBasicBlock *MBB,
+ MachineInstr &Root,
+ SmallVector<int, 16> &Patterns) {
long PrevLatencyDiff = std::numeric_limits<long>::max();
(void)PrevLatencyDiff; // Variable is used in assert only.
for (auto P : Patterns) {
@@ -590,7 +570,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
while (BlockIter != MBB->end()) {
auto &MI = *BlockIter++;
- SmallVector<MachineCombinerPattern, 16> Patterns;
+ SmallVector<int, 16> Patterns;
// The motivating example is:
//
// MUL Other MUL_op1 MUL_op2 Other
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 9fbd516acea8e1..45710579d50df3 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -919,7 +919,7 @@ bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
// instruction is known to not increase the critical path, then don't match
// that pattern.
bool TargetInstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) const {
bool Commute;
if (isReassociationCandidate(Root, Commute)) {
@@ -941,14 +941,14 @@ bool TargetInstrInfo::getMachineCombinerPatterns(
}
/// Return true when a code sequence can improve loop throughput.
-bool
-TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
- return false;
+bool TargetInstrInfo::isThroughputPattern(int Pattern) const { return false; }
+
+CombinerObjective TargetInstrInfo::getCombinerObjective(int Pattern) const {
+ return CombinerObjective::Default;
}
std::pair<unsigned, unsigned>
-TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern,
- const MachineInstr &Root,
+TargetInstrInfo::getReassociationOpcodes(int Pattern, const MachineInstr &Root,
const MachineInstr &Prev) const {
bool AssocCommutRoot = isAssociativeAndCommutative(Root);
bool AssocCommutPrev = isAssociativeAndCommutative(Prev);
@@ -1036,7 +1036,7 @@ TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern,
// Return a pair of boolean flags showing if the new root and new prev operands
// must be swapped. See visual example of the rule in
// TargetInstrInfo::getReassociationOpcodes.
-static std::pair<bool, bool> mustSwapOperands(MachineCombinerPattern Pattern) {
+static std::pair<bool, bool> mustSwapOperands(int Pattern) {
switch (Pattern) {
default:
llvm_unreachable("Unexpected pattern");
@@ -1054,8 +1054,7 @@ static std::pair<bool, bool> mustSwapOperands(MachineCombinerPattern Pattern) {
/// Attempt the reassociation transformation to reduce critical path length.
/// See the above comments before getMachineCombinerPatterns().
void TargetInstrInfo::reassociateOps(
- MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
+ MachineInstr &Root, MachineInstr &Prev, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
@@ -1177,8 +1176,7 @@ void TargetInstrInfo::reassociateOps(
}
void TargetInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 22687b0e31c284..ac7710bfd05ca4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -6056,7 +6056,7 @@ bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
/// Find instructions that can be turned into madd.
static bool getMaddPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns) {
+ SmallVectorImpl<int> &Patterns) {
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
@@ -6076,22 +6076,21 @@ static bool getMaddPatterns(MachineInstr &Root,
Opc = NewOpc;
}
- auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
- MachineCombinerPattern Pattern) {
+ auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, int Pattern) {
if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
Patterns.push_back(Pattern);
Found = true;
}
};
- auto setVFound = [&](int Opcode, int Operand, MachineCombinerPattern Pattern) {
+ auto setVFound = [&](int Opcode, int Operand, int Pattern) {
if (canCombine(MBB, Root.getOperand(Operand), Opcode)) {
Patterns.push_back(Pattern);
Found = true;
}
};
- typedef MachineCombinerPattern MCP;
+ typedef AArch64MachineCombinerPattern MCP;
switch (Opc) {
default:
@@ -6196,8 +6195,7 @@ static bool getMaddPatterns(MachineInstr &Root,
/// Floating-Point Support
/// Find instructions that can be turned into madd.
-static bool getFMAPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns) {
+static bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns) {
if (!isCombineInstrCandidateFP(Root))
return false;
@@ -6205,8 +6203,7 @@ static bool getFMAPatterns(MachineInstr &Root,
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
- auto Match = [&](int Opcode, int Operand,
- MachineCombinerPattern Pattern) -> bool {
+ auto Match = [&](int Opcode, int Operand, int Pattern) -> bool {
if (canCombineWithFMUL(MBB, Root.getOperand(Operand), Opcode)) {
Patterns.push_back(Pattern);
return true;
@@ -6214,7 +6211,7 @@ static bool getFMAPatterns(MachineInstr &Root,
return false;
};
- typedef MachineCombinerPattern MCP;
+ typedef AArch64MachineCombinerPattern MCP;
switch (Root.getOpcode()) {
default:
@@ -6340,12 +6337,11 @@ static bool getFMAPatterns(MachineInstr &Root,
}
static bool getFMULPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns) {
+ SmallVectorImpl<int> &Patterns) {
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
- auto Match = [&](unsigned Opcode, int Operand,
- MachineCombinerPattern Pattern) -> bool {
+ auto Match = [&](unsigned Opcode, int Operand, int Pattern) -> bool {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
MachineOperand &MO = Root.getOperand(Operand);
MachineInstr *MI = nullptr;
@@ -6362,7 +6358,7 @@ static bool getFMULPatterns(MachineInstr &Root,
return false;
};
- typedef MachineCombinerPattern MCP;
+ typedef AArch64MachineCombinerPattern MCP;
switch (Root.getOpcode()) {
default:
@@ -6393,12 +6389,12 @@ static bool getFMULPatterns(MachineInstr &Root,
}
static bool getFNEGPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns) {
+ SmallVectorImpl<int> &Patterns) {
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
- auto Match = [&](unsigned Opcode, MachineCombinerPattern Pattern) -> bool {
+ auto Match = [&](unsigned Opcode, int Pattern) -> bool {
MachineOperand &MO = Root.getOperand(1);
MachineInstr *MI = MRI.getUniqueVRegDef(MO.getReg());
if (MI != nullptr && (MI->getOpcode() == Opcode) &&
@@ -6417,9 +6413,9 @@ static bool getFNEGPatterns(MachineInstr &Root,
default:
break;
case AArch64::FNEGDr:
- return Match(AArch64::FMADDDrrr, MachineCombinerPattern::FNMADD);
+ return Match(AArch64::FMADDDrrr, AArch64MachineCombinerPattern::FNMADD);
case AArch64::FNEGSr:
- return Match(AArch64::FMADDSrrr, MachineCombinerPattern::FNMADD);
+ return Match(AArch64::FMADDSrrr, AArch64MachineCombinerPattern::FNMADD);
}
return false;
@@ -6428,116 +6424,115 @@ static bool getFNEGPatterns(MachineInstr &Root,
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
-bool AArch64InstrInfo::isThroughputPattern(
- MachineCombinerPattern Pattern) const {
+bool AArch64InstrInfo::isThroughputPattern(int Pattern) const {
switch (Pattern) {
default:
break;
- case MachineCombinerPattern::FMULADDH_OP1:
- case MachineCombinerPattern::FMULADDH_OP2:
- case MachineCombinerPattern::FMULSUBH_OP1:
- case MachineCombinerPattern::FMULSUBH_OP2:
- case MachineCombinerPattern::FMULADDS_OP1:
- case MachineCombinerPattern::FMULADDS_OP2:
- case MachineCombinerPattern::FMULSUBS_OP1:
- case MachineCombinerPattern::FMULSUBS_OP2:
- case MachineCombinerPattern::FMULADDD_OP1:
- case MachineCombinerPattern::FMULADDD_OP2:
- case MachineCombinerPattern::FMULSUBD_OP1:
- case MachineCombinerPattern::FMULSUBD_OP2:
- case MachineCombinerPattern::FNMULSUBH_OP1:
- case MachineCombinerPattern::FNMULSUBS_OP1:
- case MachineCombinerPattern::FNMULSUBD_OP1:
- case MachineCombinerPattern::FMLAv4i16_indexed_OP1:
- case MachineCombinerPattern::FMLAv4i16_indexed_OP2:
- case MachineCombinerPattern::FMLAv8i16_indexed_OP1:
- case MachineCombinerPattern::FMLAv8i16_indexed_OP2:
- case MachineCombinerPattern::FMLAv1i32_indexed_OP1:
- case MachineCombinerPattern::FMLAv1i32_indexed_OP2:
- case MachineCombinerPattern::FMLAv1i64_indexed_OP1:
- case MachineCombinerPattern::FMLAv1i64_indexed_OP2:
- case MachineCombinerPattern::FMLAv4f16_OP2:
- case MachineCombinerPattern::FMLAv4f16_OP1:
- case MachineCombinerPattern::FMLAv8f16_OP1:
- case MachineCombinerPattern::FMLAv8f16_OP2:
- case MachineCombinerPattern::FMLAv2f32_OP2:
- case MachineCombinerPattern::FMLAv2f32_OP1:
- case MachineCombinerPattern::FMLAv2f64_OP1:
- case MachineCombinerPattern::FMLAv2f64_OP2:
- case MachineCombinerPattern::FMLAv2i32_indexed_OP1:
- case MachineCombinerPattern::FMLAv2i32_indexed_OP2:
- case MachineCombinerPattern::FMLAv2i64_indexed_OP1:
- case MachineCombinerPattern::FMLAv2i64_indexed_OP2:
- case MachineCombinerPattern::FMLAv4f32_OP1:
- case MachineCombinerPattern::FMLAv4f32_OP2:
- case MachineCombinerPattern::FMLAv4i32_indexed_OP1:
- case MachineCombinerPattern::FMLAv4i32_indexed_OP2:
- case MachineCombinerPattern::FMLSv4i16_indexed_OP1:
- case MachineCombinerPattern::FMLSv4i16_indexed_OP2:
- case MachineCombinerPattern::FMLSv8i16_indexed_OP1:
- case MachineCombinerPattern::FMLSv8i16_indexed_OP2:
- case MachineCombinerPattern::FMLSv1i32_indexed_OP2:
- case MachineCombinerPattern::FMLSv1i64_indexed_OP2:
- case MachineCombinerPattern::FMLSv2i32_indexed_OP2:
- case MachineCombinerPattern::FMLSv2i64_indexed_OP2:
- case MachineCombinerPattern::FMLSv4f16_OP1:
- case MachineCombinerPattern::FMLSv4f16_OP2:
- case MachineCombinerPattern::FMLSv8f16_OP1:
- case MachineCombinerPattern::FMLSv8f16_OP2:
- case MachineCombinerPattern::FMLSv2f32_OP2:
- case MachineCombinerPattern::FMLSv2f64_OP2:
- case MachineCombinerPattern::FMLSv4i32_indexed_OP2:
- case MachineCombinerPattern::FMLSv4f32_OP2:
- case MachineCombinerPattern::FMULv2i32_indexed_OP1:
- case MachineCombinerPattern::FMULv2i32_indexed_OP2:
- case MachineCombinerPattern::FMULv2i64_indexed_OP1:
- case MachineCombinerPattern::FMULv2i64_indexed_OP2:
- case MachineCombinerPattern::FMULv4i16_indexed_OP1:
- case MachineCombinerPattern::FMULv4i16_indexed_OP2:
- case MachineCombinerPattern::FMULv4i32_indexed_OP1:
- case MachineCombinerPattern::FMULv4i32_indexed_OP2:
- case MachineCombinerPattern::FMULv8i16_indexed_OP1:
- case MachineCombinerPattern::FMULv8i16_indexed_OP2:
- case MachineCombinerPattern::MULADDv8i8_OP1:
- case MachineCombinerPattern::MULADDv8i8_OP2:
- case MachineCombinerPattern::MULADDv16i8_OP1:
- case MachineCombinerPattern::MULADDv16i8_OP2:
- case MachineCombinerPattern::MULADDv4i16_OP1:
- case MachineCombinerPattern::MULADDv4i16_OP2:
- case MachineCombinerPattern::MULADDv8i16_OP1:
- case MachineCombinerPattern::MULADDv8i16_OP2:
- case MachineCombinerPattern::MULADDv2i32_OP1:
- case MachineCombinerPattern::MULADDv2i32_OP2:
- case MachineCombinerPattern::MULADDv4i32_OP1:
- case MachineCombinerPattern::MULADDv4i32_OP2:
- case MachineCombinerPattern::MULSUBv8i8_OP1:
- case MachineCombinerPattern::MULSUBv8i8_OP2:
- case MachineCombinerPattern::MULSUBv16i8_OP1:
- case MachineCombinerPattern::MULSUBv16i8_OP2:
- case MachineCombinerPattern::MULSUBv4i16_OP1:
- case MachineCombinerPattern::MULSUBv4i16_OP2:
- case MachineCombinerPattern::MULSUBv8i16_OP1:
- case MachineCombinerPattern::MULSUBv8i16_OP2:
- case MachineCombinerPattern::MULSUBv2i32_OP1:
- case MachineCombinerPattern::MULSUBv2i32_OP2:
- case MachineCombinerPattern::MULSUBv4i32_OP1:
- case MachineCombinerPattern::MULSUBv4i32_OP2:
- case MachineCombinerPattern::MULADDv4i16_indexed_OP1:
- case MachineCombinerPattern::MULADDv4i16_indexed_OP2:
- case MachineCombinerPattern::MULADDv8i16_indexed_OP1:
- case MachineCombinerPattern::MULADDv8i16_indexed_OP2:
- case MachineCombinerPattern::MULADDv2i32_indexed_OP1:
- case MachineCombinerPattern::MULADDv2i32_indexed_OP2:
- case MachineCombinerPattern::MULADDv4i32_indexed_OP1:
- case MachineCombinerPattern::MULADDv4i32_indexed_OP2:
- case MachineCombinerPattern::MULSUBv4i16_indexed_OP1:
- case MachineCombinerPattern::MULSUBv4i16_indexed_OP2:
- case MachineCombinerPattern::MULSUBv8i16_indexed_OP1:
- case MachineCombinerPattern::MULSUBv8i16_indexed_OP2:
- case MachineCombinerPattern::MULSUBv2i32_indexed_OP1:
- case MachineCombinerPattern::MULSUBv2i32_indexed_OP2:
- case MachineCombinerPattern::MULSUBv4i32_indexed_OP1:
- case MachineCombinerPattern::MULSUBv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMULADDH_OP1:
+ case AArch64MachineCombinerPattern::FMULADDH_OP2:
+ case AArch64MachineCombinerPattern::FMULSUBH_OP1:
+ case AArch64MachineCombinerPattern::FMULSUBH_OP2:
+ case AArch64MachineCombinerPattern::FMULADDS_OP1:
+ case AArch64MachineCombinerPattern::FMULADDS_OP2:
+ case AArch64MachineCombinerPattern::FMULSUBS_OP1:
+ case AArch64MachineCombinerPattern::FMULSUBS_OP2:
+ case AArch64MachineCombinerPattern::FMULADDD_OP1:
+ case AArch64MachineCombinerPattern::FMULADDD_OP2:
+ case AArch64MachineCombinerPattern::FMULSUBD_OP1:
+ case AArch64MachineCombinerPattern::FMULSUBD_OP2:
+ case AArch64MachineCombinerPattern::FNMULSUBH_OP1:
+ case AArch64MachineCombinerPattern::FNMULSUBS_OP1:
+ case AArch64MachineCombinerPattern::FNMULSUBD_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4f16_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4f16_OP1:
+ case AArch64MachineCombinerPattern::FMLAv8f16_OP1:
+ case AArch64MachineCombinerPattern::FMLAv8f16_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2f32_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2f32_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2f64_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2f64_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4f32_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4f32_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv1i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv1i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4f16_OP1:
+ case AArch64MachineCombinerPattern::FMLSv4f16_OP2:
+ case AArch64MachineCombinerPattern::FMLSv8f16_OP1:
+ case AArch64MachineCombinerPattern::FMLSv8f16_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2f32_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2f64_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4f32_OP2:
+ case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv8i8_OP1:
+ case AArch64MachineCombinerPattern::MULADDv8i8_OP2:
+ case AArch64MachineCombinerPattern::MULADDv16i8_OP1:
+ case AArch64MachineCombinerPattern::MULADDv16i8_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i16_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i16_OP2:
+ case AArch64MachineCombinerPattern::MULADDv8i16_OP1:
+ case AArch64MachineCombinerPattern::MULADDv8i16_OP2:
+ case AArch64MachineCombinerPattern::MULADDv2i32_OP1:
+ case AArch64MachineCombinerPattern::MULADDv2i32_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i32_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i32_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv8i8_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv8i8_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv16i8_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv16i8_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP2:
return true;
} // end switch (Pattern)
return false;
@@ -6545,8 +6540,7 @@ bool AArch64InstrInfo::isThroughputPattern(
/// Find other MI combine patterns.
static bool getMiscPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns)
-{
+ SmallVectorImpl<int> &Patterns) {
// A - (B + C) ==> (A - B) - C or (A - C) - B
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
@@ -6570,21 +6564,31 @@ static bool getMiscPatterns(MachineInstr &Root,
canCombine(MBB, Root.getOperand(2), AArch64::ADDSWrr) ||
canCombine(MBB, Root.getOperand(2), AArch64::ADDXrr) ||
canCombine(MBB, Root.getOperand(2), AArch64::ADDSXrr)) {
- Patterns.push_back(MachineCombinerPattern::SUBADD_OP1);
- Patterns.push_back(MachineCombinerPattern::SUBADD_OP2);
+ Patterns.push_back(AArch64MachineCombinerPattern::SUBADD_OP1);
+ Patterns.push_back(AArch64MachineCombinerPattern::SUBADD_OP2);
return true;
}
return false;
}
+CombinerObjective AArch64InstrInfo::getCombinerObjective(int Pattern) const {
+ switch (Pattern) {
+ case AArch64MachineCombinerPattern::SUBADD_OP1:
+ case AArch64MachineCombinerPattern::SUBADD_OP2:
+ return CombinerObjective::MustReduceDepth;
+ default:
+ return TargetInstrInfo::getCombinerObjective(Pattern);
+ }
+}
+
/// Return true when there is potentially a faster code sequence for an
/// instruction chain ending in \p Root. All potential patterns are listed in
/// the \p Pattern vector. Pattern should be sorted in priority order since the
/// pattern evaluator stops checking as soon as it finds a faster sequence.
bool AArch64InstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) const {
// Integer patterns
if (getMaddPatterns(Root, Patterns))
@@ -6943,8 +6947,7 @@ genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
/// this function generates the instructions that could replace the
/// original code sequence
void AArch64InstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
MachineBasicBlock &MBB = *Root.getParent();
@@ -6961,25 +6964,25 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
DelInstrs, InstrIdxForVirtReg);
return;
- case MachineCombinerPattern::SUBADD_OP1:
+ case AArch64MachineCombinerPattern::SUBADD_OP1:
// A - (B + C)
// ==> (A - B) - C
genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 1,
InstrIdxForVirtReg);
break;
- case MachineCombinerPattern::SUBADD_OP2:
+ case AArch64MachineCombinerPattern::SUBADD_OP2:
// A - (B + C)
// ==> (A - C) - B
genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 2,
InstrIdxForVirtReg);
break;
- case MachineCombinerPattern::MULADDW_OP1:
- case MachineCombinerPattern::MULADDX_OP1:
+ case AArch64MachineCombinerPattern::MULADDW_OP1:
+ case AArch64MachineCombinerPattern::MULADDX_OP1:
// MUL I=A,B,0
// ADD R,I,C
// ==> MADD R,A,B,C
// --- Create(MADD);
- if (Pattern == MachineCombinerPattern::MULADDW_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::MULADDW_OP1) {
Opc = AArch64::MADDWrrr;
RC = &AArch64::GPR32RegClass;
} else {
@@ -6988,13 +6991,13 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDW_OP2:
- case MachineCombinerPattern::MULADDX_OP2:
+ case AArch64MachineCombinerPattern::MULADDW_OP2:
+ case AArch64MachineCombinerPattern::MULADDX_OP2:
// MUL I=A,B,0
// ADD R,C,I
// ==> MADD R,A,B,C
// --- Create(MADD);
- if (Pattern == MachineCombinerPattern::MULADDW_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::MULADDW_OP2) {
Opc = AArch64::MADDWrrr;
RC = &AArch64::GPR32RegClass;
} else {
@@ -7003,8 +7006,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDWI_OP1:
- case MachineCombinerPattern::MULADDXI_OP1: {
+ case AArch64MachineCombinerPattern::MULADDWI_OP1:
+ case AArch64MachineCombinerPattern::MULADDXI_OP1: {
// MUL I=A,B,0
// ADD R,I,Imm
// ==> MOV V, Imm
@@ -7012,7 +7015,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
// --- Create(MADD);
const TargetRegisterClass *OrrRC;
unsigned BitSize, OrrOpc, ZeroReg;
- if (Pattern == MachineCombinerPattern::MULADDWI_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::MULADDWI_OP1) {
OrrOpc = AArch64::ORRWri;
OrrRC = &AArch64::GPR32spRegClass;
BitSize = 32;
@@ -7065,8 +7068,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
break;
}
- case MachineCombinerPattern::MULSUBW_OP1:
- case MachineCombinerPattern::MULSUBX_OP1: {
+ case AArch64MachineCombinerPattern::MULSUBW_OP1:
+ case AArch64MachineCombinerPattern::MULSUBX_OP1: {
// MUL I=A,B,0
// SUB R,I, C
// ==> SUB V, 0, C
@@ -7074,7 +7077,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
// --- Create(MADD);
const TargetRegisterClass *SubRC;
unsigned SubOpc, ZeroReg;
- if (Pattern == MachineCombinerPattern::MULSUBW_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::MULSUBW_OP1) {
SubOpc = AArch64::SUBWrr;
SubRC = &AArch64::GPR32spRegClass;
ZeroReg = AArch64::WZR;
@@ -7098,13 +7101,13 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC);
break;
}
- case MachineCombinerPattern::MULSUBW_OP2:
- case MachineCombinerPattern::MULSUBX_OP2:
+ case AArch64MachineCombinerPattern::MULSUBW_OP2:
+ case AArch64MachineCombinerPattern::MULSUBX_OP2:
// MUL I=A,B,0
// SUB R,C,I
// ==> MSUB R,A,B,C (computes C - A*B)
// --- Create(MSUB);
- if (Pattern == MachineCombinerPattern::MULSUBW_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::MULSUBW_OP2) {
Opc = AArch64::MSUBWrrr;
RC = &AArch64::GPR32RegClass;
} else {
@@ -7113,8 +7116,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBWI_OP1:
- case MachineCombinerPattern::MULSUBXI_OP1: {
+ case AArch64MachineCombinerPattern::MULSUBWI_OP1:
+ case AArch64MachineCombinerPattern::MULSUBXI_OP1: {
// MUL I=A,B,0
// SUB R,I, Imm
// ==> MOV V, -Imm
@@ -7122,7 +7125,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
// --- Create(MADD);
const TargetRegisterClass *OrrRC;
unsigned BitSize, OrrOpc, ZeroReg;
- if (Pattern == MachineCombinerPattern::MULSUBWI_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::MULSUBWI_OP1) {
OrrOpc = AArch64::ORRWri;
OrrRC = &AArch64::GPR32spRegClass;
BitSize = 32;
@@ -7175,318 +7178,318 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
break;
}
- case MachineCombinerPattern::MULADDv8i8_OP1:
+ case AArch64MachineCombinerPattern::MULADDv8i8_OP1:
Opc = AArch64::MLAv8i8;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv8i8_OP2:
+ case AArch64MachineCombinerPattern::MULADDv8i8_OP2:
Opc = AArch64::MLAv8i8;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv16i8_OP1:
+ case AArch64MachineCombinerPattern::MULADDv16i8_OP1:
Opc = AArch64::MLAv16i8;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv16i8_OP2:
+ case AArch64MachineCombinerPattern::MULADDv16i8_OP2:
Opc = AArch64::MLAv16i8;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i16_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i16_OP1:
Opc = AArch64::MLAv4i16;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i16_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i16_OP2:
Opc = AArch64::MLAv4i16;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv8i16_OP1:
+ case AArch64MachineCombinerPattern::MULADDv8i16_OP1:
Opc = AArch64::MLAv8i16;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv8i16_OP2:
+ case AArch64MachineCombinerPattern::MULADDv8i16_OP2:
Opc = AArch64::MLAv8i16;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv2i32_OP1:
+ case AArch64MachineCombinerPattern::MULADDv2i32_OP1:
Opc = AArch64::MLAv2i32;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv2i32_OP2:
+ case AArch64MachineCombinerPattern::MULADDv2i32_OP2:
Opc = AArch64::MLAv2i32;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i32_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i32_OP1:
Opc = AArch64::MLAv4i32;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i32_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i32_OP2:
Opc = AArch64::MLAv4i32;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv8i8_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv8i8_OP1:
Opc = AArch64::MLAv8i8;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i8,
RC);
break;
- case MachineCombinerPattern::MULSUBv8i8_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv8i8_OP2:
Opc = AArch64::MLSv8i8;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv16i8_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv16i8_OP1:
Opc = AArch64::MLAv16i8;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv16i8,
RC);
break;
- case MachineCombinerPattern::MULSUBv16i8_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv16i8_OP2:
Opc = AArch64::MLSv16i8;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv4i16_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_OP1:
Opc = AArch64::MLAv4i16;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16,
RC);
break;
- case MachineCombinerPattern::MULSUBv4i16_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_OP2:
Opc = AArch64::MLSv4i16;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv8i16_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_OP1:
Opc = AArch64::MLAv8i16;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16,
RC);
break;
- case MachineCombinerPattern::MULSUBv8i16_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_OP2:
Opc = AArch64::MLSv8i16;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv2i32_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_OP1:
Opc = AArch64::MLAv2i32;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32,
RC);
break;
- case MachineCombinerPattern::MULSUBv2i32_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_OP2:
Opc = AArch64::MLSv2i32;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv4i32_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_OP1:
Opc = AArch64::MLAv4i32;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32,
RC);
break;
- case MachineCombinerPattern::MULSUBv4i32_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_OP2:
Opc = AArch64::MLSv4i32;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP1:
Opc = AArch64::MLAv4i16_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP2:
Opc = AArch64::MLAv4i16_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP1:
Opc = AArch64::MLAv8i16_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP2:
Opc = AArch64::MLAv8i16_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP1:
Opc = AArch64::MLAv2i32_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP2:
Opc = AArch64::MLAv2i32_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP1:
Opc = AArch64::MLAv4i32_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::MULADDv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP2:
Opc = AArch64::MLAv4i32_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP1:
Opc = AArch64::MLAv4i16_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16,
RC);
break;
- case MachineCombinerPattern::MULSUBv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP2:
Opc = AArch64::MLSv4i16_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP1:
Opc = AArch64::MLAv8i16_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16,
RC);
break;
- case MachineCombinerPattern::MULSUBv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP2:
Opc = AArch64::MLSv8i16_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP1:
Opc = AArch64::MLAv2i32_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32,
RC);
break;
- case MachineCombinerPattern::MULSUBv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP2:
Opc = AArch64::MLSv2i32_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::MULSUBv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP1:
Opc = AArch64::MLAv4i32_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs,
InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32,
RC);
break;
- case MachineCombinerPattern::MULSUBv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP2:
Opc = AArch64::MLSv4i32_indexed;
RC = &AArch64::FPR128RegClass;
MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
// Floating Point Support
- case MachineCombinerPattern::FMULADDH_OP1:
+ case AArch64MachineCombinerPattern::FMULADDH_OP1:
Opc = AArch64::FMADDHrrr;
RC = &AArch64::FPR16RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FMULADDS_OP1:
+ case AArch64MachineCombinerPattern::FMULADDS_OP1:
Opc = AArch64::FMADDSrrr;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FMULADDD_OP1:
+ case AArch64MachineCombinerPattern::FMULADDD_OP1:
Opc = AArch64::FMADDDrrr;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FMULADDH_OP2:
+ case AArch64MachineCombinerPattern::FMULADDH_OP2:
Opc = AArch64::FMADDHrrr;
RC = &AArch64::FPR16RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::FMULADDS_OP2:
+ case AArch64MachineCombinerPattern::FMULADDS_OP2:
Opc = AArch64::FMADDSrrr;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::FMULADDD_OP2:
+ case AArch64MachineCombinerPattern::FMULADDD_OP2:
Opc = AArch64::FMADDDrrr;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::FMLAv1i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP1:
Opc = AArch64::FMLAv1i32_indexed;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv1i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP2:
Opc = AArch64::FMLAv1i32_indexed;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv1i64_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP1:
Opc = AArch64::FMLAv1i64_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv1i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP2:
Opc = AArch64::FMLAv1i64_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP1:
RC = &AArch64::FPR64RegClass;
Opc = AArch64::FMLAv4i16_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv4f16_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4f16_OP1:
RC = &AArch64::FPR64RegClass;
Opc = AArch64::FMLAv4f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Accumulator);
break;
- case MachineCombinerPattern::FMLAv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP2:
RC = &AArch64::FPR64RegClass;
Opc = AArch64::FMLAv4i16_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv4f16_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4f16_OP2:
RC = &AArch64::FPR64RegClass;
Opc = AArch64::FMLAv4f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Accumulator);
break;
- case MachineCombinerPattern::FMLAv2i32_indexed_OP1:
- case MachineCombinerPattern::FMLAv2f32_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2f32_OP1:
RC = &AArch64::FPR64RegClass;
- if (Pattern == MachineCombinerPattern::FMLAv2i32_indexed_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP1) {
Opc = AArch64::FMLAv2i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed);
@@ -7496,10 +7499,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
FMAInstKind::Accumulator);
}
break;
- case MachineCombinerPattern::FMLAv2i32_indexed_OP2:
- case MachineCombinerPattern::FMLAv2f32_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2f32_OP2:
RC = &AArch64::FPR64RegClass;
- if (Pattern == MachineCombinerPattern::FMLAv2i32_indexed_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP2) {
Opc = AArch64::FMLAv2i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
@@ -7510,35 +7513,35 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
- case MachineCombinerPattern::FMLAv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP1:
RC = &AArch64::FPR128RegClass;
Opc = AArch64::FMLAv8i16_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv8f16_OP1:
+ case AArch64MachineCombinerPattern::FMLAv8f16_OP1:
RC = &AArch64::FPR128RegClass;
Opc = AArch64::FMLAv8f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Accumulator);
break;
- case MachineCombinerPattern::FMLAv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP2:
RC = &AArch64::FPR128RegClass;
Opc = AArch64::FMLAv8i16_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLAv8f16_OP2:
+ case AArch64MachineCombinerPattern::FMLAv8f16_OP2:
RC = &AArch64::FPR128RegClass;
Opc = AArch64::FMLAv8f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Accumulator);
break;
- case MachineCombinerPattern::FMLAv2i64_indexed_OP1:
- case MachineCombinerPattern::FMLAv2f64_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv2f64_OP1:
RC = &AArch64::FPR128RegClass;
- if (Pattern == MachineCombinerPattern::FMLAv2i64_indexed_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP1) {
Opc = AArch64::FMLAv2i64_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed);
@@ -7548,10 +7551,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
FMAInstKind::Accumulator);
}
break;
- case MachineCombinerPattern::FMLAv2i64_indexed_OP2:
- case MachineCombinerPattern::FMLAv2f64_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv2f64_OP2:
RC = &AArch64::FPR128RegClass;
- if (Pattern == MachineCombinerPattern::FMLAv2i64_indexed_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP2) {
Opc = AArch64::FMLAv2i64_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
@@ -7562,10 +7565,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
- case MachineCombinerPattern::FMLAv4i32_indexed_OP1:
- case MachineCombinerPattern::FMLAv4f32_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMLAv4f32_OP1:
RC = &AArch64::FPR128RegClass;
- if (Pattern == MachineCombinerPattern::FMLAv4i32_indexed_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP1) {
Opc = AArch64::FMLAv4i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed);
@@ -7576,10 +7579,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
- case MachineCombinerPattern::FMLAv4i32_indexed_OP2:
- case MachineCombinerPattern::FMLAv4f32_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLAv4f32_OP2:
RC = &AArch64::FPR128RegClass;
- if (Pattern == MachineCombinerPattern::FMLAv4i32_indexed_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP2) {
Opc = AArch64::FMLAv4i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
@@ -7590,70 +7593,70 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
- case MachineCombinerPattern::FMULSUBH_OP1:
+ case AArch64MachineCombinerPattern::FMULSUBH_OP1:
Opc = AArch64::FNMSUBHrrr;
RC = &AArch64::FPR16RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FMULSUBS_OP1:
+ case AArch64MachineCombinerPattern::FMULSUBS_OP1:
Opc = AArch64::FNMSUBSrrr;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FMULSUBD_OP1:
+ case AArch64MachineCombinerPattern::FMULSUBD_OP1:
Opc = AArch64::FNMSUBDrrr;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FNMULSUBH_OP1:
+ case AArch64MachineCombinerPattern::FNMULSUBH_OP1:
Opc = AArch64::FNMADDHrrr;
RC = &AArch64::FPR16RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FNMULSUBS_OP1:
+ case AArch64MachineCombinerPattern::FNMULSUBS_OP1:
Opc = AArch64::FNMADDSrrr;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FNMULSUBD_OP1:
+ case AArch64MachineCombinerPattern::FNMULSUBD_OP1:
Opc = AArch64::FNMADDDrrr;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC);
break;
- case MachineCombinerPattern::FMULSUBH_OP2:
+ case AArch64MachineCombinerPattern::FMULSUBH_OP2:
Opc = AArch64::FMSUBHrrr;
RC = &AArch64::FPR16RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::FMULSUBS_OP2:
+ case AArch64MachineCombinerPattern::FMULSUBS_OP2:
Opc = AArch64::FMSUBSrrr;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::FMULSUBD_OP2:
+ case AArch64MachineCombinerPattern::FMULSUBD_OP2:
Opc = AArch64::FMSUBDrrr;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC);
break;
- case MachineCombinerPattern::FMLSv1i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv1i32_indexed_OP2:
Opc = AArch64::FMLSv1i32_indexed;
RC = &AArch64::FPR32RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLSv1i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv1i64_indexed_OP2:
Opc = AArch64::FMLSv1i64_indexed;
RC = &AArch64::FPR64RegClass;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLSv4f16_OP1:
- case MachineCombinerPattern::FMLSv4i16_indexed_OP1: {
+ case AArch64MachineCombinerPattern::FMLSv4f16_OP1:
+ case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP1: {
RC = &AArch64::FPR64RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
@@ -7661,7 +7664,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
- if (Pattern == MachineCombinerPattern::FMLSv4f16_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv4f16_OP1) {
Opc = AArch64::FMLAv4f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Accumulator, &NewVR);
@@ -7672,23 +7675,23 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
}
- case MachineCombinerPattern::FMLSv4f16_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4f16_OP2:
RC = &AArch64::FPR64RegClass;
Opc = AArch64::FMLSv4f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Accumulator);
break;
- case MachineCombinerPattern::FMLSv4i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP2:
RC = &AArch64::FPR64RegClass;
Opc = AArch64::FMLSv4i16_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLSv2f32_OP2:
- case MachineCombinerPattern::FMLSv2i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2f32_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP2:
RC = &AArch64::FPR64RegClass;
- if (Pattern == MachineCombinerPattern::FMLSv2i32_indexed_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP2) {
Opc = AArch64::FMLSv2i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
@@ -7699,8 +7702,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
- case MachineCombinerPattern::FMLSv8f16_OP1:
- case MachineCombinerPattern::FMLSv8i16_indexed_OP1: {
+ case AArch64MachineCombinerPattern::FMLSv8f16_OP1:
+ case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP1: {
RC = &AArch64::FPR128RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
@@ -7708,7 +7711,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
- if (Pattern == MachineCombinerPattern::FMLSv8f16_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv8f16_OP1) {
Opc = AArch64::FMLAv8f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Accumulator, &NewVR);
@@ -7719,23 +7722,23 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
}
- case MachineCombinerPattern::FMLSv8f16_OP2:
+ case AArch64MachineCombinerPattern::FMLSv8f16_OP2:
RC = &AArch64::FPR128RegClass;
Opc = AArch64::FMLSv8f16;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Accumulator);
break;
- case MachineCombinerPattern::FMLSv8i16_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP2:
RC = &AArch64::FPR128RegClass;
Opc = AArch64::FMLSv8i16_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
break;
- case MachineCombinerPattern::FMLSv2f64_OP2:
- case MachineCombinerPattern::FMLSv2i64_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2f64_OP2:
+ case AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP2:
RC = &AArch64::FPR128RegClass;
- if (Pattern == MachineCombinerPattern::FMLSv2i64_indexed_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP2) {
Opc = AArch64::FMLSv2i64_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
@@ -7746,10 +7749,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
- case MachineCombinerPattern::FMLSv4f32_OP2:
- case MachineCombinerPattern::FMLSv4i32_indexed_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4f32_OP2:
+ case AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP2:
RC = &AArch64::FPR128RegClass;
- if (Pattern == MachineCombinerPattern::FMLSv4i32_indexed_OP2) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP2) {
Opc = AArch64::FMLSv4i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC,
FMAInstKind::Indexed);
@@ -7759,8 +7762,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
FMAInstKind::Accumulator);
}
break;
- case MachineCombinerPattern::FMLSv2f32_OP1:
- case MachineCombinerPattern::FMLSv2i32_indexed_OP1: {
+ case AArch64MachineCombinerPattern::FMLSv2f32_OP1:
+ case AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP1: {
RC = &AArch64::FPR64RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
@@ -7768,7 +7771,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
- if (Pattern == MachineCombinerPattern::FMLSv2i32_indexed_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP1) {
Opc = AArch64::FMLAv2i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed, &NewVR);
@@ -7779,8 +7782,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
}
- case MachineCombinerPattern::FMLSv4f32_OP1:
- case MachineCombinerPattern::FMLSv4i32_indexed_OP1: {
+ case AArch64MachineCombinerPattern::FMLSv4f32_OP1:
+ case AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP1: {
RC = &AArch64::FPR128RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
@@ -7788,7 +7791,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
- if (Pattern == MachineCombinerPattern::FMLSv4i32_indexed_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP1) {
Opc = AArch64::FMLAv4i32_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed, &NewVR);
@@ -7799,8 +7802,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
}
- case MachineCombinerPattern::FMLSv2f64_OP1:
- case MachineCombinerPattern::FMLSv2i64_indexed_OP1: {
+ case AArch64MachineCombinerPattern::FMLSv2f64_OP1:
+ case AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP1: {
RC = &AArch64::FPR128RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
@@ -7808,7 +7811,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
- if (Pattern == MachineCombinerPattern::FMLSv2i64_indexed_OP1) {
+ if (Pattern == AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP1) {
Opc = AArch64::FMLAv2i64_indexed;
MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC,
FMAInstKind::Indexed, &NewVR);
@@ -7819,47 +7822,52 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
}
break;
}
- case MachineCombinerPattern::FMULv2i32_indexed_OP1:
- case MachineCombinerPattern::FMULv2i32_indexed_OP2: {
+ case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP2: {
unsigned IdxDupOp =
- (Pattern == MachineCombinerPattern::FMULv2i32_indexed_OP1) ? 1 : 2;
+ (Pattern == AArch64MachineCombinerPattern::FMULv2i32_indexed_OP1) ? 1
+ : 2;
genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv2i32_indexed,
&AArch64::FPR128RegClass, MRI);
break;
}
- case MachineCombinerPattern::FMULv2i64_indexed_OP1:
- case MachineCombinerPattern::FMULv2i64_indexed_OP2: {
+ case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP2: {
unsigned IdxDupOp =
- (Pattern == MachineCombinerPattern::FMULv2i64_indexed_OP1) ? 1 : 2;
+ (Pattern == AArch64MachineCombinerPattern::FMULv2i64_indexed_OP1) ? 1
+ : 2;
genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv2i64_indexed,
&AArch64::FPR128RegClass, MRI);
break;
}
- case MachineCombinerPattern::FMULv4i16_indexed_OP1:
- case MachineCombinerPattern::FMULv4i16_indexed_OP2: {
+ case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP2: {
unsigned IdxDupOp =
- (Pattern == MachineCombinerPattern::FMULv4i16_indexed_OP1) ? 1 : 2;
+ (Pattern == AArch64MachineCombinerPattern::FMULv4i16_indexed_OP1) ? 1
+ : 2;
genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv4i16_indexed,
&AArch64::FPR128_loRegClass, MRI);
break;
}
- case MachineCombinerPattern::FMULv4i32_indexed_OP1:
- case MachineCombinerPattern::FMULv4i32_indexed_OP2: {
+ case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP2: {
unsigned IdxDupOp =
- (Pattern == MachineCombinerPattern::FMULv4i32_indexed_OP1) ? 1 : 2;
+ (Pattern == AArch64MachineCombinerPattern::FMULv4i32_indexed_OP1) ? 1
+ : 2;
genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv4i32_indexed,
&AArch64::FPR128RegClass, MRI);
break;
}
- case MachineCombinerPattern::FMULv8i16_indexed_OP1:
- case MachineCombinerPattern::FMULv8i16_indexed_OP2: {
+ case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP1:
+ case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP2: {
unsigned IdxDupOp =
- (Pattern == MachineCombinerPattern::FMULv8i16_indexed_OP1) ? 1 : 2;
+ (Pattern == AArch64MachineCombinerPattern::FMULv8i16_indexed_OP1) ? 1
+ : 2;
genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv8i16_indexed,
&AArch64::FPR128_loRegClass, MRI);
break;
}
- case MachineCombinerPattern::FNMADD: {
+ case AArch64MachineCombinerPattern::FNMADD: {
MUL = genFNegatedMAD(MF, MRI, TII, Root, InsInstrs);
break;
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 2f10f80f4bdf70..7181e4afa55940 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -33,6 +33,146 @@ static const MachineMemOperand::Flags MOStridedAccess =
#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
+// AArch64 MachineCombiner patterns
+enum AArch64MachineCombinerPattern {
+ // These are patterns used to reduce the length of dependence chain.
+ SUBADD_OP1 = MachineCombinerPattern::TARGET_PATTERN_START,
+ SUBADD_OP2,
+
+ // These are multiply-add patterns matched by the AArch64 machine combiner.
+ MULADDW_OP1,
+ MULADDW_OP2,
+ MULSUBW_OP1,
+ MULSUBW_OP2,
+ MULADDWI_OP1,
+ MULSUBWI_OP1,
+ MULADDX_OP1,
+ MULADDX_OP2,
+ MULSUBX_OP1,
+ MULSUBX_OP2,
+ MULADDXI_OP1,
+ MULSUBXI_OP1,
+ // NEON integers vectors
+ MULADDv8i8_OP1,
+ MULADDv8i8_OP2,
+ MULADDv16i8_OP1,
+ MULADDv16i8_OP2,
+ MULADDv4i16_OP1,
+ MULADDv4i16_OP2,
+ MULADDv8i16_OP1,
+ MULADDv8i16_OP2,
+ MULADDv2i32_OP1,
+ MULADDv2i32_OP2,
+ MULADDv4i32_OP1,
+ MULADDv4i32_OP2,
+
+ MULSUBv8i8_OP1,
+ MULSUBv8i8_OP2,
+ MULSUBv16i8_OP1,
+ MULSUBv16i8_OP2,
+ MULSUBv4i16_OP1,
+ MULSUBv4i16_OP2,
+ MULSUBv8i16_OP1,
+ MULSUBv8i16_OP2,
+ MULSUBv2i32_OP1,
+ MULSUBv2i32_OP2,
+ MULSUBv4i32_OP1,
+ MULSUBv4i32_OP2,
+
+ MULADDv4i16_indexed_OP1,
+ MULADDv4i16_indexed_OP2,
+ MULADDv8i16_indexed_OP1,
+ MULADDv8i16_indexed_OP2,
+ MULADDv2i32_indexed_OP1,
+ MULADDv2i32_indexed_OP2,
+ MULADDv4i32_indexed_OP1,
+ MULADDv4i32_indexed_OP2,
+
+ MULSUBv4i16_indexed_OP1,
+ MULSUBv4i16_indexed_OP2,
+ MULSUBv8i16_indexed_OP1,
+ MULSUBv8i16_indexed_OP2,
+ MULSUBv2i32_indexed_OP1,
+ MULSUBv2i32_indexed_OP2,
+ MULSUBv4i32_indexed_OP1,
+ MULSUBv4i32_indexed_OP2,
+
+ // Floating Point
+ FMULADDH_OP1,
+ FMULADDH_OP2,
+ FMULSUBH_OP1,
+ FMULSUBH_OP2,
+ FMULADDS_OP1,
+ FMULADDS_OP2,
+ FMULSUBS_OP1,
+ FMULSUBS_OP2,
+ FMULADDD_OP1,
+ FMULADDD_OP2,
+ FMULSUBD_OP1,
+ FMULSUBD_OP2,
+ FNMULSUBH_OP1,
+ FNMULSUBS_OP1,
+ FNMULSUBD_OP1,
+ FMLAv1i32_indexed_OP1,
+ FMLAv1i32_indexed_OP2,
+ FMLAv1i64_indexed_OP1,
+ FMLAv1i64_indexed_OP2,
+ FMLAv4f16_OP1,
+ FMLAv4f16_OP2,
+ FMLAv8f16_OP1,
+ FMLAv8f16_OP2,
+ FMLAv2f32_OP2,
+ FMLAv2f32_OP1,
+ FMLAv2f64_OP1,
+ FMLAv2f64_OP2,
+ FMLAv4i16_indexed_OP1,
+ FMLAv4i16_indexed_OP2,
+ FMLAv8i16_indexed_OP1,
+ FMLAv8i16_indexed_OP2,
+ FMLAv2i32_indexed_OP1,
+ FMLAv2i32_indexed_OP2,
+ FMLAv2i64_indexed_OP1,
+ FMLAv2i64_indexed_OP2,
+ FMLAv4f32_OP1,
+ FMLAv4f32_OP2,
+ FMLAv4i32_indexed_OP1,
+ FMLAv4i32_indexed_OP2,
+ FMLSv1i32_indexed_OP2,
+ FMLSv1i64_indexed_OP2,
+ FMLSv4f16_OP1,
+ FMLSv4f16_OP2,
+ FMLSv8f16_OP1,
+ FMLSv8f16_OP2,
+ FMLSv2f32_OP1,
+ FMLSv2f32_OP2,
+ FMLSv2f64_OP1,
+ FMLSv2f64_OP2,
+ FMLSv4i16_indexed_OP1,
+ FMLSv4i16_indexed_OP2,
+ FMLSv8i16_indexed_OP1,
+ FMLSv8i16_indexed_OP2,
+ FMLSv2i32_indexed_OP1,
+ FMLSv2i32_indexed_OP2,
+ FMLSv2i64_indexed_OP1,
+ FMLSv2i64_indexed_OP2,
+ FMLSv4f32_OP1,
+ FMLSv4f32_OP2,
+ FMLSv4i32_indexed_OP1,
+ FMLSv4i32_indexed_OP2,
+
+ FMULv2i32_indexed_OP1,
+ FMULv2i32_indexed_OP2,
+ FMULv2i64_indexed_OP1,
+ FMULv2i64_indexed_OP2,
+ FMULv4i16_indexed_OP1,
+ FMULv4i16_indexed_OP2,
+ FMULv4i32_indexed_OP1,
+ FMULv4i32_indexed_OP2,
+ FMULv8i16_indexed_OP1,
+ FMULv8i16_indexed_OP2,
+
+ FNMADD,
+};
class AArch64InstrInfo final : public AArch64GenInstrInfo {
const AArch64RegisterInfo RI;
const AArch64Subtarget &Subtarget;
@@ -283,17 +423,17 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
const MachineRegisterInfo *MRI) const override;
bool optimizeCondBranch(MachineInstr &MI) const override;
+ CombinerObjective getCombinerObjective(int Pattern) const override;
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
- bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
+ bool isThroughputPattern(int Pattern) const override;
/// Return true when there is potentially a faster code sequence
/// for an instruction chain ending in ``Root``. All potential patterns are
/// listed in the ``Patterns`` array.
- bool
- getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const override;
+ bool getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const override;
/// Return true when Inst is associative and commutative so that it can be
/// reassociated. If Invert is true, then the inverse of Inst operation must
/// be checked.
@@ -302,7 +442,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
/// When getMachineCombinerPatterns() finds patterns, this function generates
/// the instructions that could replace the original code sequence
void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
+ MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 5f5eb31a5a85fa..2084374579b669 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -348,9 +348,9 @@ int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
// register with D. After the transformation, A and D must be assigned with
// same hardware register due to TIE attribute of FMA instructions.
//
-bool PPCInstrInfo::getFMAPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const {
+bool PPCInstrInfo::getFMAPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const {
MachineBasicBlock *MBB = Root.getParent();
const MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
const TargetRegisterInfo *TRI = &getRegisterInfo();
@@ -476,7 +476,7 @@ bool PPCInstrInfo::getFMAPatterns(
if (isLoadFromConstantPool(MULInstrL) && IsUsedOnceR &&
IsReassociableAddOrSub(*MULInstrR, InfoArrayIdxFSubInst)) {
LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BCA\n");
- Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BCA);
+ Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XY_BCA);
return true;
}
@@ -484,7 +484,7 @@ bool PPCInstrInfo::getFMAPatterns(
if ((isLoadFromConstantPool(MULInstrR) && IsUsedOnceL &&
IsReassociableAddOrSub(*MULInstrL, InfoArrayIdxFSubInst))) {
LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BAC\n");
- Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BAC);
+ Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XY_BAC);
return true;
}
}
@@ -511,12 +511,12 @@ bool PPCInstrInfo::getFMAPatterns(
MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA);
AddOpIdx = -1;
if (IsReassociableFMA(*Leaf, AddOpIdx, MulOpIdx, true)) {
- Patterns.push_back(MachineCombinerPattern::REASSOC_XMM_AMM_BMM);
+ Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM);
LLVM_DEBUG(dbgs() << "add pattern REASSOC_XMM_AMM_BMM\n");
return true;
}
if (IsReassociableAddOrSub(*Leaf, InfoArrayIdxFAddInst)) {
- Patterns.push_back(MachineCombinerPattern::REASSOC_XY_AMM_BMM);
+ Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM);
LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_AMM_BMM\n");
return true;
}
@@ -524,7 +524,7 @@ bool PPCInstrInfo::getFMAPatterns(
}
void PPCInstrInfo::finalizeInsInstrs(
- MachineInstr &Root, MachineCombinerPattern &P,
+ MachineInstr &Root, int &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {
assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!");
@@ -542,12 +542,12 @@ void PPCInstrInfo::finalizeInsInstrs(
// For now we only need to fix up placeholder for register pressure reduce
// patterns.
Register ConstReg = 0;
- switch (P) {
- case MachineCombinerPattern::REASSOC_XY_BCA:
+ switch (Pattern) {
+ case PPCMachineCombinerPattern::REASSOC_XY_BCA:
ConstReg =
TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), MRI);
break;
- case MachineCombinerPattern::REASSOC_XY_BAC:
+ case PPCMachineCombinerPattern::REASSOC_XY_BAC:
ConstReg =
TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx + 1).getReg(), MRI);
break;
@@ -737,9 +737,22 @@ PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const {
return nullptr;
}
-bool PPCInstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const {
+CombinerObjective PPCInstrInfo::getCombinerObjective(int Pattern) const {
+ switch (Pattern) {
+ case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM:
+ case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM:
+ return CombinerObjective::MustReduceDepth;
+ case PPCMachineCombinerPattern::REASSOC_XY_BCA:
+ case PPCMachineCombinerPattern::REASSOC_XY_BAC:
+ return CombinerObjective::MustReduceRegisterPressure;
+ default:
+ return TargetInstrInfo::getCombinerObjective(Pattern);
+ }
+}
+
+bool PPCInstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const {
// Using the machine combiner in this way is potentially expensive, so
// restrict to when aggressive optimizations are desired.
if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOptLevel::Aggressive)
@@ -753,15 +766,14 @@ bool PPCInstrInfo::getMachineCombinerPatterns(
}
void PPCInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
switch (Pattern) {
- case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
- case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
- case MachineCombinerPattern::REASSOC_XY_BCA:
- case MachineCombinerPattern::REASSOC_XY_BAC:
+ case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM:
+ case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM:
+ case PPCMachineCombinerPattern::REASSOC_XY_BCA:
+ case PPCMachineCombinerPattern::REASSOC_XY_BAC:
reassociateFMA(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg);
break;
default:
@@ -773,8 +785,7 @@ void PPCInstrInfo::genAlternativeCodeSequence(
}
void PPCInstrInfo::reassociateFMA(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
MachineFunction *MF = Root.getMF();
@@ -790,8 +801,8 @@ void PPCInstrInfo::reassociateFMA(
assert(Idx >= 0 && "Root must be a FMA instruction");
bool IsILPReassociate =
- (Pattern == MachineCombinerPattern::REASSOC_XY_AMM_BMM) ||
- (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM);
+ (Pattern == PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM) ||
+ (Pattern == PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM);
uint16_t AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx];
uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx];
@@ -801,18 +812,18 @@ void PPCInstrInfo::reassociateFMA(
switch (Pattern) {
default:
llvm_unreachable("not recognized pattern!");
- case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
- case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
+ case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM:
+ case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM:
Prev = MRI.getUniqueVRegDef(Root.getOperand(AddOpIdx).getReg());
Leaf = MRI.getUniqueVRegDef(Prev->getOperand(AddOpIdx).getReg());
break;
- case MachineCombinerPattern::REASSOC_XY_BAC: {
+ case PPCMachineCombinerPattern::REASSOC_XY_BAC: {
Register MULReg =
TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), &MRI);
Leaf = MRI.getVRegDef(MULReg);
break;
}
- case MachineCombinerPattern::REASSOC_XY_BCA: {
+ case PPCMachineCombinerPattern::REASSOC_XY_BCA: {
Register MULReg = TRI->lookThruCopyLike(
Root.getOperand(FirstMulOpIdx + 1).getReg(), &MRI);
Leaf = MRI.getVRegDef(MULReg);
@@ -853,10 +864,10 @@ void PPCInstrInfo::reassociateFMA(
if (IsILPReassociate)
GetFMAInstrInfo(*Prev, RegM21, RegM22, RegA21, KillM21, KillM22, KillA21);
- if (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM) {
+ if (Pattern == PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM) {
GetFMAInstrInfo(*Leaf, RegM11, RegM12, RegA11, KillM11, KillM12, KillA11);
GetOperandInfo(Leaf->getOperand(AddOpIdx), RegX, KillX);
- } else if (Pattern == MachineCombinerPattern::REASSOC_XY_AMM_BMM) {
+ } else if (Pattern == PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM) {
GetOperandInfo(Leaf->getOperand(1), RegX, KillX);
GetOperandInfo(Leaf->getOperand(2), RegY, KillY);
} else {
@@ -881,7 +892,7 @@ void PPCInstrInfo::reassociateFMA(
}
Register NewVRD = 0;
- if (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM) {
+ if (Pattern == PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM) {
NewVRD = MRI.createVirtualRegister(RC);
InstrIdxForVirtReg.insert(std::make_pair(NewVRD, 2));
}
@@ -901,7 +912,7 @@ void PPCInstrInfo::reassociateFMA(
switch (Pattern) {
default:
llvm_unreachable("not recognized pattern!");
- case MachineCombinerPattern::REASSOC_XY_AMM_BMM: {
+ case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM: {
// Create new instructions for insertion.
MachineInstrBuilder MINewB =
BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB)
@@ -936,7 +947,7 @@ void PPCInstrInfo::reassociateFMA(
InsInstrs.push_back(MINewC);
break;
}
- case MachineCombinerPattern::REASSOC_XMM_AMM_BMM: {
+ case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM: {
assert(NewVRD && "new FMA register not created!");
// Create new instructions for insertion.
MachineInstrBuilder MINewA =
@@ -980,11 +991,11 @@ void PPCInstrInfo::reassociateFMA(
InsInstrs.push_back(MINewC);
break;
}
- case MachineCombinerPattern::REASSOC_XY_BAC:
- case MachineCombinerPattern::REASSOC_XY_BCA: {
+ case PPCMachineCombinerPattern::REASSOC_XY_BAC:
+ case PPCMachineCombinerPattern::REASSOC_XY_BCA: {
Register VarReg;
bool KillVarReg = false;
- if (Pattern == MachineCombinerPattern::REASSOC_XY_BCA) {
+ if (Pattern == PPCMachineCombinerPattern::REASSOC_XY_BCA) {
VarReg = RegM31;
KillVarReg = KillM31;
} else {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 045932dc0d3ba1..ef17aca9ad784b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -85,6 +85,19 @@ enum SpillOpcodeKey {
SOK_LastOpcodeSpill // This must be last on the enum.
};
+// PPC MachineCombiner patterns
+enum PPCMachineCombinerPattern {
+ // These are patterns matched by the PowerPC to reassociate FMA chains.
+ REASSOC_XY_AMM_BMM = MachineCombinerPattern::TARGET_PATTERN_START,
+ REASSOC_XMM_AMM_BMM,
+
+ // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
+ // reduce register pressure.
+ REASSOC_XY_BCA,
+ REASSOC_XY_BAC,
+
+};
+
// Define list of load and store spill opcodes.
#define NoInstr PPC::INSTRUCTION_LIST_END
#define Pwr8LoadOpcodes \
@@ -224,7 +237,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
unsigned getSpillIndex(const TargetRegisterClass *RC) const;
int16_t getFMAOpIdxInfo(unsigned Opcode) const;
- void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
+ void reassociateFMA(MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
@@ -350,7 +363,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// When getMachineCombinerPatterns() finds patterns, this function generates
/// the instructions that could replace the original code sequence
void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
+ MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
@@ -358,15 +371,16 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// Return true when there is potentially a faster code sequence for a fma
/// chain ending in \p Root. All potential patterns are output in the \p
/// P array.
- bool getFMAPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &P,
+ bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) const;
+ CombinerObjective getCombinerObjective(int Pattern) const override;
+
/// Return true when there is potentially a faster code sequence
/// for an instruction chain ending in <Root>. All potential patterns are
/// output in the <Pattern> array.
bool getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &P,
+ SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) const override;
/// On PowerPC, we leverage machine combiner pass to reduce register pressure
@@ -380,7 +394,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// Fixup the placeholders we put in genAlternativeCodeSequence() for
/// MachineCombiner.
void
- finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
+ finalizeInsInstrs(MachineInstr &Root, int &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
bool isAssociativeAndCommutative(const MachineInstr &Inst,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 153f936326a78d..d930c5dd9193e3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1557,7 +1557,7 @@ MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy() const {
}
void RISCVInstrInfo::finalizeInsInstrs(
- MachineInstr &Root, MachineCombinerPattern &P,
+ MachineInstr &Root, int &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {
int16_t FrmOpIdx =
RISCV::getNamedOperandIdx(Root.getOpcode(), RISCV::OpName::frm);
@@ -1745,10 +1745,9 @@ static bool canCombineFPFusedMultiply(const MachineInstr &Root,
return RISCV::hasEqualFRM(Root, *MI);
}
-static bool
-getFPFusedMultiplyPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) {
+static bool getFPFusedMultiplyPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) {
unsigned Opc = Root.getOpcode();
bool IsFAdd = isFADD(Opc);
if (!IsFAdd && !isFSUB(Opc))
@@ -1756,27 +1755,38 @@ getFPFusedMultiplyPatterns(MachineInstr &Root,
bool Added = false;
if (canCombineFPFusedMultiply(Root, Root.getOperand(1),
DoRegPressureReduce)) {
- Patterns.push_back(IsFAdd ? MachineCombinerPattern::FMADD_AX
- : MachineCombinerPattern::FMSUB);
+ Patterns.push_back(IsFAdd ? RISCVMachineCombinerPattern::FMADD_AX
+ : RISCVMachineCombinerPattern::FMSUB);
Added = true;
}
if (canCombineFPFusedMultiply(Root, Root.getOperand(2),
DoRegPressureReduce)) {
- Patterns.push_back(IsFAdd ? MachineCombinerPattern::FMADD_XA
- : MachineCombinerPattern::FNMSUB);
+ Patterns.push_back(IsFAdd ? RISCVMachineCombinerPattern::FMADD_XA
+ : RISCVMachineCombinerPattern::FNMSUB);
Added = true;
}
return Added;
}
-static bool getFPPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
+static bool getFPPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) {
return getFPFusedMultiplyPatterns(Root, Patterns, DoRegPressureReduce);
}
+CombinerObjective RISCVInstrInfo::getCombinerObjective(int Pattern) const {
+ switch (Pattern) {
+ case RISCVMachineCombinerPattern::FMADD_AX:
+ case RISCVMachineCombinerPattern::FMADD_XA:
+ case RISCVMachineCombinerPattern::FMSUB:
+ case RISCVMachineCombinerPattern::FNMSUB:
+ return CombinerObjective::MustReduceDepth;
+ default:
+ return TargetInstrInfo::getCombinerObjective(Pattern);
+ }
+}
+
bool RISCVInstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<int> &Patterns,
bool DoRegPressureReduce) const {
if (getFPPatterns(Root, Patterns, DoRegPressureReduce))
@@ -1786,8 +1796,7 @@ bool RISCVInstrInfo::getMachineCombinerPatterns(
DoRegPressureReduce);
}
-static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc,
- MachineCombinerPattern Pattern) {
+static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, int Pattern) {
switch (RootOpc) {
default:
llvm_unreachable("Unexpected opcode");
@@ -1798,32 +1807,32 @@ static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc,
case RISCV::FADD_D:
return RISCV::FMADD_D;
case RISCV::FSUB_H:
- return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_H
- : RISCV::FNMSUB_H;
+ return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_H
+ : RISCV::FNMSUB_H;
case RISCV::FSUB_S:
- return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_S
- : RISCV::FNMSUB_S;
+ return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_S
+ : RISCV::FNMSUB_S;
case RISCV::FSUB_D:
- return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_D
- : RISCV::FNMSUB_D;
+ return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_D
+ : RISCV::FNMSUB_D;
}
}
-static unsigned getAddendOperandIdx(MachineCombinerPattern Pattern) {
+static unsigned getAddendOperandIdx(int Pattern) {
switch (Pattern) {
default:
llvm_unreachable("Unexpected pattern");
- case MachineCombinerPattern::FMADD_AX:
- case MachineCombinerPattern::FMSUB:
+ case RISCVMachineCombinerPattern::FMADD_AX:
+ case RISCVMachineCombinerPattern::FMSUB:
return 2;
- case MachineCombinerPattern::FMADD_XA:
- case MachineCombinerPattern::FNMSUB:
+ case RISCVMachineCombinerPattern::FMADD_XA:
+ case RISCVMachineCombinerPattern::FNMSUB:
return 1;
}
}
static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
- MachineCombinerPattern Pattern,
+ int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs) {
MachineFunction *MF = Root.getMF();
@@ -1865,8 +1874,7 @@ static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
}
void RISCVInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
@@ -1875,14 +1883,14 @@ void RISCVInstrInfo::genAlternativeCodeSequence(
TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
DelInstrs, InstrIdxForVirtReg);
return;
- case MachineCombinerPattern::FMADD_AX:
- case MachineCombinerPattern::FMSUB: {
+ case RISCVMachineCombinerPattern::FMADD_AX:
+ case RISCVMachineCombinerPattern::FMSUB: {
MachineInstr &Prev = *MRI.getVRegDef(Root.getOperand(1).getReg());
combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
return;
}
- case MachineCombinerPattern::FMADD_XA:
- case MachineCombinerPattern::FNMSUB: {
+ case RISCVMachineCombinerPattern::FMADD_XA:
+ case RISCVMachineCombinerPattern::FNMSUB: {
MachineInstr &Prev = *MRI.getVRegDef(Root.getOperand(2).getReg());
combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
return;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 3470012d1518ea..7f312ac75f8bd0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -49,6 +49,14 @@ unsigned getBrCond(CondCode CC);
} // end of namespace RISCVCC
+// RISCV MachineCombiner patterns
+enum RISCVMachineCombinerPattern {
+ FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START,
+ FMADD_XA,
+ FMSUB,
+ FNMSUB,
+};
+
class RISCVInstrInfo : public RISCVGenInstrInfo {
public:
@@ -238,17 +246,18 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
- bool
- getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const override;
+ CombinerObjective getCombinerObjective(int Pattern) const override;
+
+ bool getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const override;
void
- finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
+ finalizeInsInstrs(MachineInstr &Root, int &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
+ MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index a5b2e4895eded2..d56e05d6f90888 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -10577,9 +10577,9 @@ void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
}
}
-bool X86InstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const {
+bool X86InstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const {
unsigned Opc = Root.getOpcode();
switch (Opc) {
case X86::VPDPWSSDrr:
@@ -10587,7 +10587,7 @@ bool X86InstrInfo::getMachineCombinerPatterns(
case X86::VPDPWSSDYrr:
case X86::VPDPWSSDYrm: {
if (!Subtarget.hasFastDPWSSD()) {
- Patterns.push_back(MachineCombinerPattern::DPWSSD);
+ Patterns.push_back(X86MachineCombinerPattern::DPWSSD);
return true;
}
break;
@@ -10599,8 +10599,8 @@ bool X86InstrInfo::getMachineCombinerPatterns(
case X86::VPDPWSSDZr:
case X86::VPDPWSSDZm: {
if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) {
- Patterns.push_back(MachineCombinerPattern::DPWSSD);
- return true;
+ Patterns.push_back(X86MachineCombinerPattern::DPWSSD);
+ return true;
}
break;
}
@@ -10700,8 +10700,7 @@ genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII,
}
void X86InstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
- SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
switch (Pattern) {
@@ -10710,7 +10709,7 @@ void X86InstrInfo::genAlternativeCodeSequence(
TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
DelInstrs, InstrIdxForVirtReg);
return;
- case MachineCombinerPattern::DPWSSD:
+ case X86MachineCombinerPattern::DPWSSD:
genAlternativeDpCodeSequence(Root, *this, InsInstrs, DelInstrs,
InstrIdxForVirtReg);
return;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index e719be0caf3ee1..51f1409b40b958 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -26,6 +26,12 @@
namespace llvm {
class X86Subtarget;
+// X86 MachineCombiner patterns
+enum X86MachineCombinerPattern {
+ // X86 VNNI
+ DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START,
+};
+
namespace X86 {
enum AsmComments {
@@ -607,16 +613,15 @@ class X86InstrInfo final : public X86GenInstrInfo {
std::optional<DestSourcePair>
isCopyInstrImpl(const MachineInstr &MI) const override;
- bool
- getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<MachineCombinerPattern> &Patterns,
- bool DoRegPressureReduce) const override;
+ bool getMachineCombinerPatterns(MachineInstr &Root,
+ SmallVectorImpl<int> &Patterns,
+ bool DoRegPressureReduce) const override;
/// When getMachineCombinerPatterns() finds potential patterns,
/// this function generates the instructions that could replace the
/// original code sequence.
void genAlternativeCodeSequence(
- MachineInstr &Root, MachineCombinerPattern Pattern,
+ MachineInstr &Root, int Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
>From c56e1f6a2ea97941dea09081a7bccf804324aae3 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Tue, 9 Apr 2024 11:41:56 +0800
Subject: [PATCH 2/2] Address comments
Created using spr 1.3.6-beta.1
---
.../llvm/CodeGen/MachineCombinerPattern.h | 2 +-
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 14 ++++----
llvm/lib/CodeGen/MachineCombiner.cpp | 20 ++++++------
llvm/lib/CodeGen/TargetInstrInfo.cpp | 19 +++++++----
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 32 +++++++++++--------
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 10 +++---
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 18 ++++++-----
llvm/lib/Target/PowerPC/PPCInstrInfo.h | 14 ++++----
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 20 ++++++------
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 10 +++---
llvm/lib/Target/X86/X86InstrInfo.cpp | 9 +++---
llvm/lib/Target/X86/X86InstrInfo.h | 6 ++--
12 files changed, 94 insertions(+), 80 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
index ed87667662663a..3428c4dde5c7fc 100644
--- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
+++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h
@@ -25,7 +25,7 @@ enum class CombinerObjective {
};
/// These are instruction patterns matched by the machine combiner pass.
-enum MachineCombinerPattern {
+enum MachineCombinerPattern : unsigned {
// These are commutative variants for reassociating a computation chain. See
// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
REASSOC_AX_BY,
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 658092e192dd33..d4a83e3753d980 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1192,7 +1192,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// \param Root - Instruction that could be combined with one of its operands
/// \param Patterns - Vector of possible combination patterns
virtual bool getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const;
/// Return true if target supports reassociation of instructions in machine
@@ -1205,17 +1205,17 @@ class TargetInstrInfo : public MCInstrInfo {
/// Fix up the placeholder we may add in genAlternativeCodeSequence().
virtual void
- finalizeInsInstrs(MachineInstr &Root, int &Pattern,
+ finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
- virtual bool isThroughputPattern(int Pattern) const;
+ virtual bool isThroughputPattern(unsigned Pattern) const;
/// Return the objective of a combiner pattern.
/// \param Pattern - combiner pattern
- virtual CombinerObjective getCombinerObjective(int Pattern) const;
+ virtual CombinerObjective getCombinerObjective(unsigned Pattern) const;
/// Return true if the input \P Inst is part of a chain of dependent ops
/// that are suitable for reassociation, otherwise return false.
@@ -1259,7 +1259,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// \param InstIdxForVirtReg - map of virtual register to instruction in
/// InsInstr that defines it
virtual void genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern,
+ MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
@@ -1273,7 +1273,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
/// reduce critical path length.
- void reassociateOps(MachineInstr &Root, MachineInstr &Prev, int Pattern,
+ void reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
@@ -1283,7 +1283,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// (new root opcode, new prev opcode) that must be used to reassociate \P
/// Root and \P Prev accoring to \P Pattern.
std::pair<unsigned, unsigned>
- getReassociationOpcodes(int Pattern, const MachineInstr &Root,
+ getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root,
const MachineInstr &Prev) const;
/// The limit on resource length extension we accept in MachineCombiner Pass.
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index f30323611ca837..ac58162bbfb420 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -104,11 +104,11 @@ class MachineCombiner : public MachineFunctionPass {
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg,
- int Pattern, bool SlackIsAccurate);
+ unsigned Pattern, bool SlackIsAccurate);
bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- int Pattern);
+ unsigned Pattern);
bool preservesResourceLen(MachineBasicBlock *MBB,
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -122,8 +122,8 @@ class MachineCombiner : public MachineFunctionPass {
MachineTraceMetrics::Trace BlockTrace);
void verifyPatternOrder(MachineBasicBlock *MBB, MachineInstr &Root,
- SmallVector<int, 16> &Patterns);
- CombinerObjective getCombinerObjective(int Pattern);
+ SmallVector<unsigned, 16> &Patterns);
+ CombinerObjective getCombinerObjective(unsigned Pattern);
};
}
@@ -290,7 +290,7 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
return NewRootLatency;
}
-CombinerObjective MachineCombiner::getCombinerObjective(int Pattern) {
+CombinerObjective MachineCombiner::getCombinerObjective(unsigned Pattern) {
// TODO: If C++ ever gets a real enum class, make this part of the
// MachineCombinerPattern class.
switch (Pattern) {
@@ -330,7 +330,7 @@ std::pair<unsigned, unsigned> MachineCombiner::getLatenciesForInstrSequences(
bool MachineCombiner::reduceRegisterPressure(
MachineInstr &Root, MachineBasicBlock *MBB,
SmallVectorImpl<MachineInstr *> &InsInstrs,
- SmallVectorImpl<MachineInstr *> &DelInstrs, int Pattern) {
+ SmallVectorImpl<MachineInstr *> &DelInstrs, unsigned Pattern) {
// FIXME: for now, we don't do any check for the register pressure patterns.
// We treat them as always profitable. But we can do better if we make
// RegPressureTracker class be aware of TIE attribute. Then we can get an
@@ -348,7 +348,7 @@ bool MachineCombiner::improvesCriticalPathLen(
MachineTraceMetrics::Trace BlockTrace,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
- DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, int Pattern,
+ DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, unsigned Pattern,
bool SlackIsAccurate) {
// Get depth and latency of NewRoot and Root.
unsigned NewRootDepth =
@@ -478,7 +478,7 @@ insertDeleteInstructions(MachineBasicBlock *MBB, MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DelInstrs,
MachineTraceMetrics::Ensemble *TraceEnsemble,
SparseSet<LiveRegUnit> &RegUnits,
- const TargetInstrInfo *TII, int Pattern,
+ const TargetInstrInfo *TII, unsigned Pattern,
bool IncrementalUpdate) {
// If we want to fix up some placeholder for some target, do it now.
// We need this because in genAlternativeCodeSequence, we have not decided the
@@ -516,7 +516,7 @@ insertDeleteInstructions(MachineBasicBlock *MBB, MachineInstr &MI,
// later patterns. This helps to discover sub-optimal pattern orderings.
void MachineCombiner::verifyPatternOrder(MachineBasicBlock *MBB,
MachineInstr &Root,
- SmallVector<int, 16> &Patterns) {
+ SmallVector<unsigned, 16> &Patterns) {
long PrevLatencyDiff = std::numeric_limits<long>::max();
(void)PrevLatencyDiff; // Variable is used in assert only.
for (auto P : Patterns) {
@@ -570,7 +570,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
while (BlockIter != MBB->end()) {
auto &MI = *BlockIter++;
- SmallVector<int, 16> Patterns;
+ SmallVector<unsigned, 16> Patterns;
// The motivating example is:
//
// MUL Other MUL_op1 MUL_op2 Other
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 45710579d50df3..7d77e5d1a1ff05 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -919,7 +919,7 @@ bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
// instruction is known to not increase the critical path, then don't match
// that pattern.
bool TargetInstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<int> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const {
bool Commute;
if (isReassociationCandidate(Root, Commute)) {
@@ -941,14 +941,18 @@ bool TargetInstrInfo::getMachineCombinerPatterns(
}
/// Return true when a code sequence can improve loop throughput.
-bool TargetInstrInfo::isThroughputPattern(int Pattern) const { return false; }
+bool TargetInstrInfo::isThroughputPattern(unsigned Pattern) const {
+ return false;
+}
-CombinerObjective TargetInstrInfo::getCombinerObjective(int Pattern) const {
+CombinerObjective
+TargetInstrInfo::getCombinerObjective(unsigned Pattern) const {
return CombinerObjective::Default;
}
std::pair<unsigned, unsigned>
-TargetInstrInfo::getReassociationOpcodes(int Pattern, const MachineInstr &Root,
+TargetInstrInfo::getReassociationOpcodes(unsigned Pattern,
+ const MachineInstr &Root,
const MachineInstr &Prev) const {
bool AssocCommutRoot = isAssociativeAndCommutative(Root);
bool AssocCommutPrev = isAssociativeAndCommutative(Prev);
@@ -1036,7 +1040,7 @@ TargetInstrInfo::getReassociationOpcodes(int Pattern, const MachineInstr &Root,
// Return a pair of boolean flags showing if the new root and new prev operands
// must be swapped. See visual example of the rule in
// TargetInstrInfo::getReassociationOpcodes.
-static std::pair<bool, bool> mustSwapOperands(int Pattern) {
+static std::pair<bool, bool> mustSwapOperands(unsigned Pattern) {
switch (Pattern) {
default:
llvm_unreachable("Unexpected pattern");
@@ -1054,7 +1058,7 @@ static std::pair<bool, bool> mustSwapOperands(int Pattern) {
/// Attempt the reassociation transformation to reduce critical path length.
/// See the above comments before getMachineCombinerPatterns().
void TargetInstrInfo::reassociateOps(
- MachineInstr &Root, MachineInstr &Prev, int Pattern,
+ MachineInstr &Root, MachineInstr &Prev, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
@@ -1176,7 +1180,8 @@ void TargetInstrInfo::reassociateOps(
}
void TargetInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, unsigned Pattern,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index ac7710bfd05ca4..331635931e0224 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -6056,7 +6056,7 @@ bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
/// Find instructions that can be turned into madd.
static bool getMaddPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns) {
+ SmallVectorImpl<unsigned> &Patterns) {
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
@@ -6076,14 +6076,15 @@ static bool getMaddPatterns(MachineInstr &Root,
Opc = NewOpc;
}
- auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, int Pattern) {
+ auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg,
+ unsigned Pattern) {
if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
Patterns.push_back(Pattern);
Found = true;
}
};
- auto setVFound = [&](int Opcode, int Operand, int Pattern) {
+ auto setVFound = [&](int Opcode, int Operand, unsigned Pattern) {
if (canCombine(MBB, Root.getOperand(Operand), Opcode)) {
Patterns.push_back(Pattern);
Found = true;
@@ -6195,7 +6196,8 @@ static bool getMaddPatterns(MachineInstr &Root,
/// Floating-Point Support
/// Find instructions that can be turned into madd.
-static bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns) {
+static bool getFMAPatterns(MachineInstr &Root,
+ SmallVectorImpl<unsigned> &Patterns) {
if (!isCombineInstrCandidateFP(Root))
return false;
@@ -6203,7 +6205,7 @@ static bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns) {
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
- auto Match = [&](int Opcode, int Operand, int Pattern) -> bool {
+ auto Match = [&](int Opcode, int Operand, unsigned Pattern) -> bool {
if (canCombineWithFMUL(MBB, Root.getOperand(Operand), Opcode)) {
Patterns.push_back(Pattern);
return true;
@@ -6337,11 +6339,11 @@ static bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns) {
}
static bool getFMULPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns) {
+ SmallVectorImpl<unsigned> &Patterns) {
MachineBasicBlock &MBB = *Root.getParent();
bool Found = false;
- auto Match = [&](unsigned Opcode, int Operand, int Pattern) -> bool {
+ auto Match = [&](unsigned Opcode, int Operand, unsigned Pattern) -> bool {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
MachineOperand &MO = Root.getOperand(Operand);
MachineInstr *MI = nullptr;
@@ -6389,12 +6391,12 @@ static bool getFMULPatterns(MachineInstr &Root,
}
static bool getFNEGPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns) {
+ SmallVectorImpl<unsigned> &Patterns) {
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
- auto Match = [&](unsigned Opcode, int Pattern) -> bool {
+ auto Match = [&](unsigned Opcode, unsigned Pattern) -> bool {
MachineOperand &MO = Root.getOperand(1);
MachineInstr *MI = MRI.getUniqueVRegDef(MO.getReg());
if (MI != nullptr && (MI->getOpcode() == Opcode) &&
@@ -6424,7 +6426,7 @@ static bool getFNEGPatterns(MachineInstr &Root,
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
-bool AArch64InstrInfo::isThroughputPattern(int Pattern) const {
+bool AArch64InstrInfo::isThroughputPattern(unsigned Pattern) const {
switch (Pattern) {
default:
break;
@@ -6540,7 +6542,7 @@ bool AArch64InstrInfo::isThroughputPattern(int Pattern) const {
/// Find other MI combine patterns.
static bool getMiscPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns) {
+ SmallVectorImpl<unsigned> &Patterns) {
// A - (B + C) ==> (A - B) - C or (A - C) - B
unsigned Opc = Root.getOpcode();
MachineBasicBlock &MBB = *Root.getParent();
@@ -6572,7 +6574,8 @@ static bool getMiscPatterns(MachineInstr &Root,
return false;
}
-CombinerObjective AArch64InstrInfo::getCombinerObjective(int Pattern) const {
+CombinerObjective
+AArch64InstrInfo::getCombinerObjective(unsigned Pattern) const {
switch (Pattern) {
case AArch64MachineCombinerPattern::SUBADD_OP1:
case AArch64MachineCombinerPattern::SUBADD_OP2:
@@ -6588,7 +6591,7 @@ CombinerObjective AArch64InstrInfo::getCombinerObjective(int Pattern) const {
/// pattern evaluator stops checking as soon as it finds a faster sequence.
bool AArch64InstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<int> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const {
// Integer patterns
if (getMaddPatterns(Root, Patterns))
@@ -6947,7 +6950,8 @@ genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
/// this function generates the instructions that could replace the
/// original code sequence
void AArch64InstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, unsigned Pattern,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
MachineBasicBlock &MBB = *Root.getParent();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 7181e4afa55940..9a2914891675c5 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -34,7 +34,7 @@ static const MachineMemOperand::Flags MOStridedAccess =
#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
// AArch64 MachineCombiner patterns
-enum AArch64MachineCombinerPattern {
+enum AArch64MachineCombinerPattern : unsigned {
// These are patterns used to reduce the length of dependence chain.
SUBADD_OP1 = MachineCombinerPattern::TARGET_PATTERN_START,
SUBADD_OP2,
@@ -423,16 +423,16 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
const MachineRegisterInfo *MRI) const override;
bool optimizeCondBranch(MachineInstr &MI) const override;
- CombinerObjective getCombinerObjective(int Pattern) const override;
+ CombinerObjective getCombinerObjective(unsigned Pattern) const override;
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
- bool isThroughputPattern(int Pattern) const override;
+ bool isThroughputPattern(unsigned Pattern) const override;
/// Return true when there is potentially a faster code sequence
/// for an instruction chain ending in ``Root``. All potential patterns are
/// listed in the ``Patterns`` array.
bool getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const override;
/// Return true when Inst is associative and commutative so that it can be
/// reassociated. If Invert is true, then the inverse of Inst operation must
@@ -442,7 +442,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
/// When getMachineCombinerPatterns() finds patterns, this function generates
/// the instructions that could replace the original code sequence
void genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern,
+ MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 2084374579b669..93874d65531aed 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -349,7 +349,7 @@ int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
// same hardware register due to TIE attribute of FMA instructions.
//
bool PPCInstrInfo::getFMAPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const {
MachineBasicBlock *MBB = Root.getParent();
const MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
@@ -524,7 +524,7 @@ bool PPCInstrInfo::getFMAPatterns(MachineInstr &Root,
}
void PPCInstrInfo::finalizeInsInstrs(
- MachineInstr &Root, int &Pattern,
+ MachineInstr &Root, unsigned &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {
assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!");
@@ -737,7 +737,7 @@ PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const {
return nullptr;
}
-CombinerObjective PPCInstrInfo::getCombinerObjective(int Pattern) const {
+CombinerObjective PPCInstrInfo::getCombinerObjective(unsigned Pattern) const {
switch (Pattern) {
case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM:
case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM:
@@ -750,9 +750,9 @@ CombinerObjective PPCInstrInfo::getCombinerObjective(int Pattern) const {
}
}
-bool PPCInstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
- bool DoRegPressureReduce) const {
+bool PPCInstrInfo::getMachineCombinerPatterns(
+ MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
+ bool DoRegPressureReduce) const {
// Using the machine combiner in this way is potentially expensive, so
// restrict to when aggressive optimizations are desired.
if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOptLevel::Aggressive)
@@ -766,7 +766,8 @@ bool PPCInstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
}
void PPCInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, unsigned Pattern,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
switch (Pattern) {
@@ -785,7 +786,8 @@ void PPCInstrInfo::genAlternativeCodeSequence(
}
void PPCInstrInfo::reassociateFMA(
- MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, unsigned Pattern,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
MachineFunction *MF = Root.getMF();
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index ef17aca9ad784b..1e2687f92c61e5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -86,7 +86,7 @@ enum SpillOpcodeKey {
};
// PPC MachineCombiner patterns
-enum PPCMachineCombinerPattern {
+enum PPCMachineCombinerPattern : unsigned {
// These are patterns matched by the PowerPC to reassociate FMA chains.
REASSOC_XY_AMM_BMM = MachineCombinerPattern::TARGET_PATTERN_START,
REASSOC_XMM_AMM_BMM,
@@ -237,7 +237,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
ArrayRef<unsigned> getLoadOpcodesForSpillArray() const;
unsigned getSpillIndex(const TargetRegisterClass *RC) const;
int16_t getFMAOpIdxInfo(unsigned Opcode) const;
- void reassociateFMA(MachineInstr &Root, int Pattern,
+ void reassociateFMA(MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
@@ -363,7 +363,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// When getMachineCombinerPatterns() finds patterns, this function generates
/// the instructions that could replace the original code sequence
void genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern,
+ MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
@@ -371,16 +371,16 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// Return true when there is potentially a faster code sequence for a fma
/// chain ending in \p Root. All potential patterns are output in the \p
/// P array.
- bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns,
+ bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const;
- CombinerObjective getCombinerObjective(int Pattern) const override;
+ CombinerObjective getCombinerObjective(unsigned Pattern) const override;
/// Return true when there is potentially a faster code sequence
/// for an instruction chain ending in <Root>. All potential patterns are
/// output in the <Pattern> array.
bool getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const override;
/// On PowerPC, we leverage machine combiner pass to reduce register pressure
@@ -394,7 +394,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// Fixup the placeholders we put in genAlternativeCodeSequence() for
/// MachineCombiner.
void
- finalizeInsInstrs(MachineInstr &Root, int &Pattern,
+ finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
bool isAssociativeAndCommutative(const MachineInstr &Inst,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d930c5dd9193e3..172a00a5d1299e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1557,7 +1557,7 @@ MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy() const {
}
void RISCVInstrInfo::finalizeInsInstrs(
- MachineInstr &Root, int &Pattern,
+ MachineInstr &Root, unsigned &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const {
int16_t FrmOpIdx =
RISCV::getNamedOperandIdx(Root.getOpcode(), RISCV::OpName::frm);
@@ -1746,7 +1746,7 @@ static bool canCombineFPFusedMultiply(const MachineInstr &Root,
}
static bool getFPFusedMultiplyPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) {
unsigned Opc = Root.getOpcode();
bool IsFAdd = isFADD(Opc);
@@ -1768,12 +1768,13 @@ static bool getFPFusedMultiplyPatterns(MachineInstr &Root,
return Added;
}
-static bool getFPPatterns(MachineInstr &Root, SmallVectorImpl<int> &Patterns,
+static bool getFPPatterns(MachineInstr &Root,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) {
return getFPFusedMultiplyPatterns(Root, Patterns, DoRegPressureReduce);
}
-CombinerObjective RISCVInstrInfo::getCombinerObjective(int Pattern) const {
+CombinerObjective RISCVInstrInfo::getCombinerObjective(unsigned Pattern) const {
switch (Pattern) {
case RISCVMachineCombinerPattern::FMADD_AX:
case RISCVMachineCombinerPattern::FMADD_XA:
@@ -1786,7 +1787,7 @@ CombinerObjective RISCVInstrInfo::getCombinerObjective(int Pattern) const {
}
bool RISCVInstrInfo::getMachineCombinerPatterns(
- MachineInstr &Root, SmallVectorImpl<int> &Patterns,
+ MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const {
if (getFPPatterns(Root, Patterns, DoRegPressureReduce))
@@ -1796,7 +1797,7 @@ bool RISCVInstrInfo::getMachineCombinerPatterns(
DoRegPressureReduce);
}
-static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, int Pattern) {
+static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, unsigned Pattern) {
switch (RootOpc) {
default:
llvm_unreachable("Unexpected opcode");
@@ -1818,7 +1819,7 @@ static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, int Pattern) {
}
}
-static unsigned getAddendOperandIdx(int Pattern) {
+static unsigned getAddendOperandIdx(unsigned Pattern) {
switch (Pattern) {
default:
llvm_unreachable("Unexpected pattern");
@@ -1832,7 +1833,7 @@ static unsigned getAddendOperandIdx(int Pattern) {
}
static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
- int Pattern,
+ unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs) {
MachineFunction *MF = Root.getMF();
@@ -1874,7 +1875,8 @@ static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
}
void RISCVInstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, unsigned Pattern,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 7f312ac75f8bd0..2f22f3e3abb830 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -50,7 +50,7 @@ unsigned getBrCond(CondCode CC);
} // end of namespace RISCVCC
// RISCV MachineCombiner patterns
-enum RISCVMachineCombinerPattern {
+enum RISCVMachineCombinerPattern : unsigned {
FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START,
FMADD_XA,
FMSUB,
@@ -246,18 +246,18 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
MachineTraceStrategy getMachineCombinerTraceStrategy() const override;
- CombinerObjective getCombinerObjective(int Pattern) const override;
+ CombinerObjective getCombinerObjective(unsigned Pattern) const override;
bool getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const override;
void
- finalizeInsInstrs(MachineInstr &Root, int &Pattern,
+ finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
void genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern,
+ MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index d56e05d6f90888..510b08f9901a22 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -10577,9 +10577,9 @@ void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
}
}
-bool X86InstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
- bool DoRegPressureReduce) const {
+bool X86InstrInfo::getMachineCombinerPatterns(
+ MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
+ bool DoRegPressureReduce) const {
unsigned Opc = Root.getOpcode();
switch (Opc) {
case X86::VPDPWSSDrr:
@@ -10700,7 +10700,8 @@ genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII,
}
void X86InstrInfo::genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs,
+ MachineInstr &Root, unsigned Pattern,
+ SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
switch (Pattern) {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 51f1409b40b958..5407ede69a91ca 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -27,7 +27,7 @@ namespace llvm {
class X86Subtarget;
// X86 MachineCombiner patterns
-enum X86MachineCombinerPattern {
+enum X86MachineCombinerPattern : unsigned {
// X86 VNNI
DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START,
};
@@ -614,14 +614,14 @@ class X86InstrInfo final : public X86GenInstrInfo {
isCopyInstrImpl(const MachineInstr &MI) const override;
bool getMachineCombinerPatterns(MachineInstr &Root,
- SmallVectorImpl<int> &Patterns,
+ SmallVectorImpl<unsigned> &Patterns,
bool DoRegPressureReduce) const override;
/// When getMachineCombinerPatterns() finds potential patterns,
/// this function generates the instructions that could replace the
/// original code sequence.
void genAlternativeCodeSequence(
- MachineInstr &Root, int Pattern,
+ MachineInstr &Root, unsigned Pattern,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
More information about the llvm-commits
mailing list