[llvm] [RISCV] Use shNadd for scalable stack offsets (PR #88062)

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``````````bash
git-clang-format --diff f5cf98c02655de50401f6547ea181efed6a4c1f1 646e509c90215405453a78c578d240590cab518a -- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index ce8fdf9384..11d0368cef 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -207,8 +207,9 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
 
     if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
         (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
-      unsigned Opc = NumOfVReg == 2 ? RISCV::SH1ADD :
-        (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
+      unsigned Opc = NumOfVReg == 2
+                         ? RISCV::SH1ADD
+                         : (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
       BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
           .addReg(ScratchReg, RegState::Kill)
           .addReg(SrcReg, getKillRegState(KillSrcReg))
@@ -216,7 +217,8 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
     } else {
       TII->mulImm(MF, MBB, II, DL, ScratchReg, NumOfVReg, Flag);
       BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
-          .addReg(SrcReg).addReg(ScratchReg, RegState::Kill)
+          .addReg(SrcReg)
+          .addReg(ScratchReg, RegState::Kill)
           .setMIFlag(Flag);
     }
     SrcReg = DestReg;

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https://github.com/llvm/llvm-project/pull/88062