[llvm] 89ebb56 - [RISCV] Resolve CHECK prefix conflict in fixed-vectors-vwsll.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 8 15:46:06 PDT 2024
Author: Craig Topper
Date: 2024-04-08T15:45:07-07:00
New Revision: 89ebb56152192e8ad535ddd11ae0f60334fd748a
URL: https://github.com/llvm/llvm-project/commit/89ebb56152192e8ad535ddd11ae0f60334fd748a
DIFF: https://github.com/llvm/llvm-project/commit/89ebb56152192e8ad535ddd11ae0f60334fd748a.diff
LOG: [RISCV] Resolve CHECK prefix conflict in fixed-vectors-vwsll.ll. NFC
riscv32 and riscv64 generate different code for one test case so we need
RV32 and RV64 CHECK lines.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
index 83d1d1b3f94c7c..59b3d752cc20f0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV64
; ==============================================================================
; i32 -> i64
@@ -499,6 +499,55 @@ define <16 x i16> @vwsll_vv_v16i16_zext(<16 x i8> %a, <16 x i8> %b) {
}
define <16 x i16> @vwsll_vx_i64_v16i16(<16 x i8> %a, i64 %b) {
+; RV32-LABEL: vwsll_vx_i64_v16i16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vmv.v.x v16, a0
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vrgather.vi v24, v16, 0
+; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vzext.vf2 v10, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vnsrl.wi v12, v24, 0
+; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vnsrl.wi v8, v12, 0
+; RV32-NEXT: vsll.vv v8, v10, v8
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vwsll_vx_i64_v16i16:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vmv.v.x v16, a0
+; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vzext.vf2 v10, v8
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vnsrl.wi v12, v16, 0
+; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vnsrl.wi v8, v12, 0
+; RV64-NEXT: vsll.vv v8, v10, v8
+; RV64-NEXT: ret
+;
+; CHECK-ZVBB-RV32-LABEL: vwsll_vx_i64_v16i16:
+; CHECK-ZVBB-RV32: # %bb.0:
+; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vmv.v.x v16, a0
+; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vrgather.vi v24, v16, 0
+; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vzext.vf2 v10, v8
+; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v12, v24, 0
+; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-ZVBB-RV32-NEXT: vsll.vv v8, v10, v8
+; CHECK-ZVBB-RV32-NEXT: ret
+;
+; CHECK-ZVBB-RV64-LABEL: vwsll_vx_i64_v16i16:
+; CHECK-ZVBB-RV64: # %bb.0:
+; CHECK-ZVBB-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-ZVBB-RV64-NEXT: vwsll.vx v10, v8, a0
+; CHECK-ZVBB-RV64-NEXT: vmv2r.v v8, v10
+; CHECK-ZVBB-RV64-NEXT: ret
%head = insertelement <8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <8 x i64> %head, <8 x i64> poison, <16 x i32> zeroinitializer
%x = zext <16 x i8> %a to <16 x i16>
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