[llvm] [X86][AVX] Fix handling of out-of-bounds shift amounts in AVX2 vector logical shift nodes #83840 (PR #86922)

[Simon Pilgrim via llvm-commits]

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@@ -47384,6 +47408,24 @@ static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG) {
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
   EVT VT = N0.getValueType();
 
+  // Exploits AVX2 VSHLV/VSRLV instructions for efficient unsigned vector shifts
+  // with out-of-bounds clamping.
+  if (N0.getOpcode() == ISD::VSELECT &&
+      supportedVectorVarShift(VT, DAG.getSubtarget<X86Subtarget>(), ISD::SHL)) {
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RKSimon wrote:

Sorry I misunderstood you're question - just add the `const X86Subtarget &Subtarget` arg to combineShiftLeft to match combineShiftRightArithmetic

https://github.com/llvm/llvm-project/pull/86922