[llvm] [Spirv][HLSL] Add OpAll lowering and float vec support (PR #87952)

[Farzon Lotfi via llvm-commits]

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@@ -164,9 +178,82 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
   return std::make_tuple(Res, CI, NewInstr);
 }
 
+std::tuple<Register, ConstantFP *, bool, unsigned>
+SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
+                                              MachineIRBuilder *MIRBuilder,
+                                              MachineInstr *I,
+                                              const SPIRVInstrInfo *TII) {
+  const Type *LLVMFloatTy;
+  LLVMContext &Ctx = CurMF->getFunction().getContext();
+  unsigned BitWidth = 32;
+  if (SpvType)
+    LLVMFloatTy = getTypeForSPIRVType(SpvType);
+  else {
+    LLVMFloatTy = Type::getFloatTy(Ctx);
+    if (MIRBuilder)
+      SpvType = getOrCreateSPIRVType(LLVMFloatTy, *MIRBuilder);
+  }
+  bool NewInstr = false;
+  // Find a constant in DT or build a new one.
+  auto *const CI = ConstantFP::get(Ctx, Val);
+  Register Res = DT.find(CI, CurMF);
+  if (!Res.isValid()) {
+    if (SpvType)
+      BitWidth = getScalarOrVectorBitWidth(SpvType);
+
+    LLT LLTy = LLT::scalar(32);
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farzonl wrote:

Same reason why we do it here:
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp#L154
and here:
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp#L288

and maybe here for undef:
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp#L1216


In the first two case  there is a long standing todo in `getOrCreateIntCompositeOrNull` to use  bitwidth, however when I changed this to use bitwidth I  get a segfault. I can open a bug for that. That is the same with the `getOrCreateConstIntReg`. I didn't spend much time to understand why as it is tangential to the change I want to make.


Since `getOrCreateConstFloatReg`and `getOrCreateFlotCompositeOrNull`  is just a float copy of `getOrCreateConstIntReg` and `getOrCreateIntCompositeOrNull`  I'm keeping the same structure.

https://github.com/llvm/llvm-project/pull/87952