[llvm] [ARM] R11 not pushed adjacent to link register with PAC-M and AAPCS f… (PR #87491)

[via llvm-commits]

================
@@ -151,6 +151,23 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
     SingleIssuePlusExtras,
   };
 
+  /// How the push and pop instructions of callee saved registers to and from
+  /// the stack should be split.
+  enum PushPopSplitVariation {
+    /// r4-r11+lr (+r12 if necessary) can be pushed in a single instruction.
+    NoSplit,
+    /// The registers need to be split into a push of r4-r7+lr and another
+    /// containing r8-r11 (+r12 if necessary). Due to Thumb1FrameLowering
+    /// having separate handling of AAPCS being enabled, and therefore r11+lr
----------------
ostannard wrote:

As above, this should be "AAPCS frame records", not just "AAPCS".

https://github.com/llvm/llvm-project/pull/87491