[llvm] [RISCV] Eliminate getVLENFactoredAmount and expose muladd [nfc] (PR #87881)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 8 03:35:40 PDT 2024
================
@@ -3052,48 +3052,37 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
#undef CASE_WIDEOP_OPCODE_LMULS
#undef CASE_WIDEOP_OPCODE_COMMON
-void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator II,
- const DebugLoc &DL, Register DestReg,
- int64_t Amount,
- MachineInstr::MIFlag Flag) const {
- assert(Amount > 0 && "There is no need to get VLEN scaled value.");
- assert(Amount % 8 == 0 &&
- "Reserve the stack by the multiple of one vector size.");
-
+void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator II, const DebugLoc &DL,
+ Register DestReg, uint32_t Amount,
+ MachineInstr::MIFlag Flag) const {
MachineRegisterInfo &MRI = MF.getRegInfo();
- assert(isInt<32>(Amount / 8) &&
- "Expect the number of vector registers within 32-bits.");
- uint32_t NumOfVReg = Amount / 8;
-
- BuildMI(MBB, II, DL, get(RISCV::PseudoReadVLENB), DestReg).setMIFlag(Flag);
- if (llvm::has_single_bit<uint32_t>(NumOfVReg)) {
- uint32_t ShiftAmount = Log2_32(NumOfVReg);
+ if (llvm::has_single_bit<uint32_t>(Amount)) {
+ uint32_t ShiftAmount = Log2_32(Amount);
if (ShiftAmount == 0)
return;
BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg)
.addReg(DestReg, RegState::Kill)
.addImm(ShiftAmount)
.setMIFlag(Flag);
} else if (STI.hasStdExtZba() &&
- ((NumOfVReg % 3 == 0 && isPowerOf2_64(NumOfVReg / 3)) ||
- (NumOfVReg % 5 == 0 && isPowerOf2_64(NumOfVReg / 5)) ||
- (NumOfVReg % 9 == 0 && isPowerOf2_64(NumOfVReg / 9)))) {
+ ((Amount % 3 == 0 && isPowerOf2_64(Amount / 3)) ||
+ (Amount % 5 == 0 && isPowerOf2_64(Amount / 5)) ||
+ (Amount % 9 == 0 && isPowerOf2_64(Amount / 9)))) {
// We can use Zba SHXADD+SLLI instructions for multiply in some cases.
unsigned Opc;
uint32_t ShiftAmount;
- if (NumOfVReg % 9 == 0) {
+ if (Amount % 9 == 0) {
Opc = RISCV::SH3ADD;
- ShiftAmount = Log2_64(NumOfVReg / 9);
- } else if (NumOfVReg % 5 == 0) {
+ ShiftAmount = Log2_64(Amount / 9);
+ } else if (Amount % 5 == 0) {
Opc = RISCV::SH2ADD;
- ShiftAmount = Log2_64(NumOfVReg / 5);
- } else if (NumOfVReg % 3 == 0) {
+ ShiftAmount = Log2_64(Amount / 5);
+ } else if (Amount % 3 == 0) {
Opc = RISCV::SH1ADD;
- ShiftAmount = Log2_64(NumOfVReg / 3);
+ ShiftAmount = Log2_64(Amount / 3);
} else {
- llvm_unreachable("Unexpected number of vregs");
+ llvm_unreachable("impied by if-clause");
----------------
lukel97 wrote:
```suggestion
llvm_unreachable("implied by if-clause");
```
https://github.com/llvm/llvm-project/pull/87881
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