[llvm] [RISCV] Use vwadd.vx for splat vector with extension (PR #87249)

[Luke Lau via llvm-commits]

================
@@ -13598,14 +13598,26 @@ struct NodeExtensionHelper {
     case RISCVISD::VZEXT_VL:
     case RISCVISD::FP_EXTEND_VL:
       return OrigOperand.getOperand(0);
+    case ISD::SPLAT_VECTOR: {
+      SDValue Op = OrigOperand.getOperand(0);
+      unsigned Opc = Op.getOpcode();
+      if (SupportsSExt && Opc == ISD::SIGN_EXTEND_INREG)
+        return Op.getOperand(0);
+
+      if (SupportsZExt && Opc == ISD::AND)
+        return Op.getOperand(0);
----------------
lukel97 wrote:

I checked this out locally, I see now that for some reason we aren't able to combine away this redundant and:

```
Optimized legalized selection DAG: %bb.0 'vwadd_vx_splat_zext:'
SelectionDAG has 15 nodes:
  t0: ch,glue = EntryToken
      t2: nxv8i32,ch = CopyFromReg t0, Register:nxv8i32 %0
          t4: i64,ch = CopyFromReg t0, Register:i64 %1
        t18: i64 = and t4, Constant:i64<4294967295>
      t22: nxv8i32 = splat_vector t18
      t20: nxv8i1 = RISCVISD::VMSET_VL Register:i64 $x0
    t23: nxv8i64 = RISCVISD::VWADDU_VL t2, t22, undef:nxv8i64, t20, Register:i64 $x0
  t15: ch,glue = CopyToReg t0, Register:nxv8i64 $v8m8, t23
  t16: ch = RISCVISD::RET_GLUE t15, Register:nxv8i64 $v8m8, t15:1
```

I think if we want to peek through it in getSource we should probably check which operand is the source and which is the constant. But it's probably better to teach DAGCombiner to fold this, or handle this ourselves as a target specific combine for splat_vector. Since I'm think simplifyDemandedBits should be able to catch this

https://github.com/llvm/llvm-project/pull/87249