[llvm] [RISCV] Use vwadd.vx for splat vector with extension (PR #87249)

[via llvm-commits]

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@@ -13598,14 +13598,26 @@ struct NodeExtensionHelper {
     case RISCVISD::VZEXT_VL:
     case RISCVISD::FP_EXTEND_VL:
       return OrigOperand.getOperand(0);
+    case ISD::SPLAT_VECTOR: {
+      SDValue Op = OrigOperand.getOperand(0);
+      unsigned Opc = Op.getOpcode();
+      if (SupportsSExt && Opc == ISD::SIGN_EXTEND_INREG)
+        return Op.getOperand(0);
+
+      if (SupportsZExt && Opc == ISD::AND)
+        return Op.getOperand(0);
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sun-jacobi wrote:

I just noticed a mistake in the test: 
```
define <vscale x 8 x i64> @vwadd_vx_splat_zext(<vscale x 8 x i32> %va, i32 %b) {
; RV64-LABEL: vwadd_vx_splat_zext:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV64-NEXT:    vwaddu.vx v16, v8, a0
; RV64-NEXT:    vmv8r.v v8, v16
; RV64-NEXT:    ret
  %sb = zext i32 %b to i64
  %head = insertelement <vscale x 8 x i64> poison, i64 %sb, i32 0
  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
  %ve = add <vscale x 8 x i64> %vc, %splat
  ret <vscale x 8 x i64> %ve
}
```

Actually at RV64, the below is valid
```
define <vscale x 8 x i64> @vwadd_vx_splat_zext(<vscale x 8 x i32> %va, i32 %b) {
; RV64-LABEL: vwadd_vx_splat_zext:
; RV64:       # %bb.0:
; RV64-NEXT:    andi	a0, a0, -1
; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV64-NEXT:    vwaddu.vx v16, v8, a0
; RV64-NEXT:    vmv8r.v v8, v16
; RV64-NEXT:    ret
  %sb = zext i32 %b to i64
  %head = insertelement <vscale x 8 x i64> poison, i64 %sb, i32 0
  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
  %ve = add <vscale x 8 x i64> %vc, %splat
  ret <vscale x 8 x i64> %ve
}
```
It is due to this unnecessary pattern match. I will fix it soon.

https://github.com/llvm/llvm-project/pull/87249