[llvm] [RISCV] Use vwadd.vx for splat vector with extension (PR #87249)

[Luke Lau via llvm-commits]

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@@ -13598,14 +13598,26 @@ struct NodeExtensionHelper {
     case RISCVISD::VZEXT_VL:
     case RISCVISD::FP_EXTEND_VL:
       return OrigOperand.getOperand(0);
+    case ISD::SPLAT_VECTOR: {
+      SDValue Op = OrigOperand.getOperand(0);
+      unsigned Opc = Op.getOpcode();
+      if (SupportsSExt && Opc == ISD::SIGN_EXTEND_INREG)
+        return Op.getOperand(0);
+
+      if (SupportsZExt && Opc == ISD::AND)
+        return Op.getOperand(0);
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lukel97 wrote:

Why do we need to look through and/sign_extend_inreg? Do they not automatically get folded away if we can SelectionDAG already knows `DAG.MaskedValueIsZero(Op, APInt::getBitsSetFrom(ScalarBits, NarrowSize))` or `DAG.ComputeMaxSignificantBits(Op) <= NarrowSize`?

https://github.com/llvm/llvm-project/pull/87249