[llvm] [RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (PR #87950)

via llvm-commits llvm-commits at lists.llvm.org
Sun Apr 7 15:54:07 PDT 2024


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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git-clang-format --diff da675b922cca3dc9a76642d792e882979a3d8c82 b4af0bbc344932f57abd148840d543a3ecdf2b6e -- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 848b6d33f7..dd25417c6a 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -259,9 +259,9 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
       Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
       TII->movImm(MBB, II, DL, ScratchReg, Val, Flag);
       BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
-        .addReg(ScratchReg, RegState::Kill)
-        .addReg(SrcReg, getKillRegState(KillSrcReg))
-        .setMIFlag(Flag);
+          .addReg(ScratchReg, RegState::Kill)
+          .addReg(SrcReg, getKillRegState(KillSrcReg))
+          .setMIFlag(Flag);
       return;
     }
   }

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https://github.com/llvm/llvm-project/pull/87950


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