[llvm] [AMDGPU] Fix implicit $vcc operands after parsing MIR (PR #87781)

[Matt Arsenault via llvm-commits]

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@@ -642,6 +642,17 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
     Policy.ShouldTrackLaneMasks = true;
 }
 
+void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const {
+  if (isWave32()) {
+    // Fix implicit $vcc operands after MIParser has verified that they match
+    // the instruction definitions.
+    for (auto &MBB : MF) {
+      for (auto &MI : MBB)
+        InstrInfo.fixImplicitOperands(MI);
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arsenm wrote:

I've been meaning to try to use HwMode to swap out all the wavesize operands by construction 

https://github.com/llvm/llvm-project/pull/87781