[llvm] [Thumb] Resolve FIXME: We can trust live-in information from successor blocks now (PR #84111)

[via llvm-commits]

https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/84111

>From f05e91a6e9ef47c72541ba9093909a164ce353e2 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 5 Mar 2024 17:35:23 -0500
Subject: [PATCH] [Thumb] Resolve FIXME: We can trust live-in information from
 successor blocks now

As the years have gone by, live-in information has been more and more consistent and reliable, especially with changing how these are calculated.
---
 llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 26 ++++++++++---------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 469340784284cb..61d0c66ed96d9f 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -566,18 +566,20 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
   }
 
   // End of block was reached.
-  if (!MBB.succ_empty()) {
-    // FIXME: Because of a bug, live registers are sometimes missing from
-    // the successor blocks' live-in sets. This means we can't trust that
-    // information and *always* have to reset at the end of a block.
-    // See PR21029.
-    if (MBBI != MBB.end()) --MBBI;
-    BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
-        .add(t1CondCodeOp(true))
-        .addReg(Base)
-        .addImm(WordOffset * 4)
-        .addImm(Pred)
-        .addReg(PredReg);
+  // Reset if Base is in the successor blocks' live-in sets.
+  for (MachineBasicBlock *Succ : MBB.successors()) {
+    for (const MachineBasicBlock::RegisterMaskPair &LI : Succ->liveins())
+      if (TRI->regsOverlap(LI.PhysReg, Base)) {
+        if (MBBI != MBB.end())
+          --MBBI;
+        BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
+            .add(t1CondCodeOp(true))
+            .addReg(Base)
+            .addImm(WordOffset * 4)
+            .addImm(Pred)
+            .addReg(PredReg);
+        break;
+      }
   }
 }