[llvm] [RISCV] Add CodeGen only version of conditional branch instructions t… (PR #87834)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 5 14:59:03 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
…hat are not relaxed by MC layer.
This is a possible fix for #<!-- -->87127.
As described in that bug -O0 implicitly adds -mrelax-all. This causes all branches to be relaxed by the MC layer to a short branch over a longer jump. On large functions, this can increase code size so much that we need to relax an unconditional branch to an indirect branch. The MC layer is not able to create an indirect branch since it needs a scratch register.
I believe this -O0 implying -mrelax-all behavior is a compile time optimization to prevent iterative relaxing fragments at -O0. By relaxing all, they will resolve in two passes through layout.
RISC-V uses the BranchRelaxation pass so we don't need MC layer relaxation for correctness on compiled code. With 1 exception, we do need to relax compressed branches to uncompressed branches.
This patch proposes to add unrelaxable CodeGenOnly branches so that the MC layer will ignore them. This keeps the compile time benefit of -mrelax-all without the size bloat.
Alternatively, we could add some flag from CodeGen to MC to disable the relaxation, but that has some layering challengs and may interact poorly with inline assembly.
Note there are still broken cases even with this patch. Relaxing compressed branches for -mrelax-all can still increase the size too much. We could maybe make BranchRelaxation aware of -mrelax-all to prevent this.
---
Patch is 54.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/87834.diff
28 Files Affected:
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp (+11)
- (modified) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp (+5-5)
- (modified) llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp (+8-8)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+18-18)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+32-8)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (+23-2)
- (modified) llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir (+13-13)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv64.mir (+13-13)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-medium-rv64.mir (+1-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv32.mir (+1-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-pic-rv64.mir (+1-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-rv32.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/jump-table-brjt-small-rv64.mir (+1-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir (+1-1)
- (modified) llvm/test/CodeGen/RISCV/branch-opt.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/copy-frameindex.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/float-select-verify.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/copyprop.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir (+22-22)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir (+3-25)
- (modified) llvm/test/CodeGen/RISCV/select-optimize-multiple.mir (+8-6)
- (modified) llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir (+2-2)
``````````diff
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 182a9c1544fd25..ceb42802b21b89 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -183,7 +183,9 @@ void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
default:
llvm_unreachable("Opcode not expected!");
case RISCV::C_BEQZ:
+ case RISCV::PseudoC_BEQZ:
case RISCV::C_BNEZ:
+ case RISCV::PseudoC_BNEZ:
case RISCV::C_J:
case RISCV::C_JAL: {
[[maybe_unused]] bool Success = RISCVRVC::uncompress(Res, Inst, STI);
@@ -358,9 +360,18 @@ unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
return RISCV::BEQ;
case RISCV::C_BNEZ:
return RISCV::BNE;
+ // Compression in RISCVAsmPrinter is not aware of branch distance so we need
+ // to uncompress the PseudoC_BEQZ/BNEZ here.
+ case RISCV::PseudoC_BEQZ:
+ return RISCV::PseudoBEQ;
+ case RISCV::PseudoC_BNEZ:
+ return RISCV::PseudoBNE;
case RISCV::C_J:
case RISCV::C_JAL: // fall through.
return RISCV::JAL;
+ // NOTE: We do not relax the CodeGenOnly PseudoBEQ and friends to
+ // PseudoLongBEQ here. They were already relaxed by the BranchRelaxation pass
+ // as needed.
case RISCV::BEQ:
return RISCV::PseudoLongBEQ;
case RISCV::BNE:
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 5bf594c0b5eae3..a01aa26f2a13cd 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -541,7 +541,7 @@ void RISCVAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
// Compare the hashes and trap if there's a mismatch.
MCSymbol *Pass = OutContext.createTempSymbol();
EmitToStreamer(*OutStreamer,
- MCInstBuilder(RISCV::BEQ)
+ MCInstBuilder(RISCV::PseudoBEQ)
.addReg(ScratchRegs[0])
.addReg(ScratchRegs[1])
.addExpr(MCSymbolRefExpr::create(Pass, OutContext)));
@@ -618,7 +618,7 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
// X7 contains tag from memory, while X6 contains tag from the pointer
OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::BNE)
+ MCInstBuilder(RISCV::PseudoBNE)
.addReg(RISCV::X7)
.addReg(RISCV::X6)
.addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
@@ -640,7 +640,7 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
MCSTI);
MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::BGEU)
+ MCInstBuilder(RISCV::PseudoBGEU)
.addReg(RISCV::X6)
.addReg(RISCV::X28)
.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
@@ -657,7 +657,7 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
.addImm(Size - 1),
MCSTI);
OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::BGE)
+ MCInstBuilder(RISCV::PseudoBGE)
.addReg(RISCV::X28)
.addReg(RISCV::X6)
.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
@@ -670,7 +670,7 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
MCSTI);
OutStreamer->emitInstruction(
- MCInstBuilder(RISCV::BEQ)
+ MCInstBuilder(RISCV::PseudoBEQ)
.addReg(RISCV::X6)
.addReg(RISCV::X7)
.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index bb772fc5da9224..eddaddbfa9ccaf 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -291,7 +291,7 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg)
.addReg(AddrReg)
.addReg(ScratchReg);
- BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
+ BuildMI(LoopMBB, DL, TII->get(RISCV::PseudoBNE))
.addReg(ScratchReg)
.addReg(RISCV::X0)
.addMBB(LoopMBB);
@@ -379,7 +379,7 @@ static void doMaskedAtomicBinOpExpansion(const RISCVInstrInfo *TII,
BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering, STI)), ScratchReg)
.addReg(AddrReg)
.addReg(ScratchReg);
- BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
+ BuildMI(LoopMBB, DL, TII->get(RISCV::PseudoBNE))
.addReg(ScratchReg)
.addReg(RISCV::X0)
.addMBB(LoopMBB);
@@ -498,7 +498,7 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
llvm_unreachable("Unexpected AtomicRMW BinOp");
case AtomicRMWInst::Max: {
insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
- BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::PseudoBGE))
.addReg(Scratch2Reg)
.addReg(IncrReg)
.addMBB(LoopTailMBB);
@@ -506,20 +506,20 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
}
case AtomicRMWInst::Min: {
insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
- BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::PseudoBGE))
.addReg(IncrReg)
.addReg(Scratch2Reg)
.addMBB(LoopTailMBB);
break;
}
case AtomicRMWInst::UMax:
- BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::PseudoBGEU))
.addReg(Scratch2Reg)
.addReg(IncrReg)
.addMBB(LoopTailMBB);
break;
case AtomicRMWInst::UMin:
- BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
+ BuildMI(LoopHeadMBB, DL, TII->get(RISCV::PseudoBGEU))
.addReg(IncrReg)
.addReg(Scratch2Reg)
.addMBB(LoopTailMBB);
@@ -539,7 +539,7 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering, STI)), Scratch1Reg)
.addReg(AddrReg)
.addReg(Scratch1Reg);
- BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
+ BuildMI(LoopTailMBB, DL, TII->get(RISCV::PseudoBNE))
.addReg(Scratch1Reg)
.addReg(RISCV::X0)
.addMBB(LoopHeadMBB);
@@ -594,7 +594,7 @@ bool tryToFoldBNEOnCmpXchgResult(MachineBasicBlock &MBB,
}
// Match BNE DestReg, MaskReg.
- if (MBBI == E || MBBI->getOpcode() != RISCV::BNE)
+ if (MBBI == E || MBBI->getOpcode() != RISCV::PseudoBNE)
return false;
Register BNEOp0 = MBBI->getOperand(0).getReg();
Register BNEOp1 = MBBI->getOperand(1).getReg();
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 279d8a435a04ca..5aa36b97393359 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17265,7 +17265,7 @@ static MachineBasicBlock *emitReadCounterWidePseudo(MachineInstr &MI,
.addImm(HiCounter)
.addReg(RISCV::X0);
- BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
+ BuildMI(LoopMBB, DL, TII->get(RISCV::PseudoBNE))
.addReg(HiReg)
.addReg(ReadAgainReg)
.addMBB(LoopMBB);
@@ -17794,7 +17794,7 @@ static MachineBasicBlock *emitFROUND(MachineInstr &MI, MachineBasicBlock *MBB,
MIB->setFlag(MachineInstr::MIFlag::NoFPExcept);
// Insert branch.
- BuildMI(MBB, DL, TII.get(RISCV::BEQ))
+ BuildMI(MBB, DL, TII.get(RISCV::PseudoBEQ))
.addReg(CmpReg)
.addReg(RISCV::X0)
.addMBB(DoneMBB);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 5582de51b17d19..d950fed07e2cda 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -876,17 +876,17 @@ static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
switch (Opc) {
default:
return RISCVCC::COND_INVALID;
- case RISCV::BEQ:
+ case RISCV::PseudoBEQ:
return RISCVCC::COND_EQ;
- case RISCV::BNE:
+ case RISCV::PseudoBNE:
return RISCVCC::COND_NE;
- case RISCV::BLT:
+ case RISCV::PseudoBLT:
return RISCVCC::COND_LT;
- case RISCV::BGE:
+ case RISCV::PseudoBGE:
return RISCVCC::COND_GE;
- case RISCV::BLTU:
+ case RISCV::PseudoBLTU:
return RISCVCC::COND_LTU;
- case RISCV::BGEU:
+ case RISCV::PseudoBGEU:
return RISCVCC::COND_GEU;
}
}
@@ -911,17 +911,17 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
default:
llvm_unreachable("Unknown condition code!");
case RISCVCC::COND_EQ:
- return RISCV::BEQ;
+ return RISCV::PseudoBEQ;
case RISCVCC::COND_NE:
- return RISCV::BNE;
+ return RISCV::PseudoBNE;
case RISCVCC::COND_LT:
- return RISCV::BLT;
+ return RISCV::PseudoBLT;
case RISCVCC::COND_GE:
- return RISCV::BGE;
+ return RISCV::PseudoBGE;
case RISCVCC::COND_LTU:
- return RISCV::BLTU;
+ return RISCV::PseudoBLTU;
case RISCVCC::COND_GEU:
- return RISCV::BGEU;
+ return RISCV::PseudoBGEU;
}
}
@@ -1294,12 +1294,12 @@ bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
switch (BranchOp) {
default:
llvm_unreachable("Unexpected opcode!");
- case RISCV::BEQ:
- case RISCV::BNE:
- case RISCV::BLT:
- case RISCV::BGE:
- case RISCV::BLTU:
- case RISCV::BGEU:
+ case RISCV::PseudoBEQ:
+ case RISCV::PseudoBNE:
+ case RISCV::PseudoBLT:
+ case RISCV::PseudoBGE:
+ case RISCV::PseudoBLTU:
+ case RISCV::PseudoBGEU:
return isIntN(13, BrOffset);
case RISCV::JAL:
case RISCV::PseudoBR:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 2cfad7f7c06110..08076f4b8566cb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -628,6 +628,17 @@ def BGE : BranchCC_rri<0b101, "bge">;
def BLTU : BranchCC_rri<0b110, "bltu">;
def BGEU : BranchCC_rri<0b111, "bgeu">;
+let isCodeGenOnly = 1 in {
+// CodeGenOnly versions of the above that are ignored by MC layer relaxing to
+// PseudoLongB*. We use the BranchRelaxation pass for CodeGen.
+def PseudoBEQ : BranchCC_rri<0b000, "beq">;
+def PseudoBNE : BranchCC_rri<0b001, "bne">;
+def PseudoBLT : BranchCC_rri<0b100, "blt">;
+def PseudoBGE : BranchCC_rri<0b101, "bge">;
+def PseudoBLTU : BranchCC_rri<0b110, "bltu">;
+def PseudoBGEU : BranchCC_rri<0b111, "bgeu">;
+}
+
let IsSignExtendingOpW = 1 in {
def LB : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
def LH : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>;
@@ -912,6 +923,19 @@ def : InstAlias<"bltz $rs, $offset",
def : InstAlias<"bgtz $rs, $offset",
(BLT X0, GPR:$rs, simm13_lsb0:$offset)>;
+def : InstAlias<"beqz $rs, $offset",
+ (PseudoBEQ GPR:$rs, X0, simm13_lsb0:$offset)>;
+def : InstAlias<"bnez $rs, $offset",
+ (PseudoBNE GPR:$rs, X0, simm13_lsb0:$offset)>;
+def : InstAlias<"blez $rs, $offset",
+ (PseudoBGE X0, GPR:$rs, simm13_lsb0:$offset)>;
+def : InstAlias<"bgez $rs, $offset",
+ (PseudoBGE GPR:$rs, X0, simm13_lsb0:$offset)>;
+def : InstAlias<"bltz $rs, $offset",
+ (PseudoBLT GPR:$rs, X0, simm13_lsb0:$offset)>;
+def : InstAlias<"bgtz $rs, $offset",
+ (PseudoBLT X0, GPR:$rs, simm13_lsb0:$offset)>;
+
// Always output the canonical mnemonic for the pseudo branch instructions.
// The GNU tools emit the canonical mnemonic for the branch pseudo instructions
// as well (e.g. "bgt" will be recognised by the assembler but never printed by
@@ -1412,16 +1436,16 @@ class BrccCompressOpt<CondCode Cond, RVInstB Inst>
(Inst (XLenVT (ADDI GPR:$lhs, (NegImm simm12:$Constant))),
(XLenVT X0), bb:$place)>;
-defm : BccPat<SETEQ, BEQ>;
-defm : BccPat<SETNE, BNE>;
-defm : BccPat<SETLT, BLT>;
-defm : BccPat<SETGE, BGE>;
-defm : BccPat<SETULT, BLTU>;
-defm : BccPat<SETUGE, BGEU>;
+defm : BccPat<SETEQ, PseudoBEQ>;
+defm : BccPat<SETNE, PseudoBNE>;
+defm : BccPat<SETLT, PseudoBLT>;
+defm : BccPat<SETGE, PseudoBGE>;
+defm : BccPat<SETULT, PseudoBLTU>;
+defm : BccPat<SETUGE, PseudoBGEU>;
let Predicates = [HasStdExtCOrZca, OptForMinSize] in {
- def : BrccCompressOpt<SETEQ, BEQ>;
- def : BrccCompressOpt<SETNE, BNE>;
+ def : BrccCompressOpt<SETEQ, PseudoBEQ>;
+ def : BrccCompressOpt<SETNE, PseudoBNE>;
}
class LongBccPseudo : Pseudo<(outs),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 18d38348f7214f..a0ef668cd86e70 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -495,6 +495,13 @@ def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
def C_BEQZ : Bcz<0b110, "c.beqz", GPRC>, Sched<[WriteJmp, ReadJmp]>;
def C_BNEZ : Bcz<0b111, "c.bnez", GPRC>, Sched<[WriteJmp, ReadJmp]>;
+// CodeGenOnly versions of the above that compress/uncompress to/from
+// PseudoBEQ/BNE.
+let isCodeGenOnly = 1 in {
+def PseudoC_BEQZ : Bcz<0b110, "c.beqz", GPRC>, Sched<[WriteJmp, ReadJmp]>;
+def PseudoC_BNEZ : Bcz<0b111, "c.bnez", GPRC>, Sched<[WriteJmp, ReadJmp]>;
+}
+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
@@ -956,14 +963,28 @@ def : CompressPat<(JAL X0, simm12_lsb0:$offset),
(C_J simm12_lsb0:$offset)>;
def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
-let isCompressOnly = true in
+def : CompressPat<(PseudoBEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
+ (PseudoC_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
+let isCompressOnly = true in {
def : CompressPat<(BEQ X0, GPRC:$rs1, simm9_lsb0:$imm),
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(PseudoBEQ X0, GPRC:$rs1, simm9_lsb0:$imm),
+ (PseudoC_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
+}
def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
-let isCompressOnly = true in
+def : CompressPat<(PseudoBNE GPRC:$rs1, X0, simm9_lsb0:$imm),
+ (PseudoC_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
+ (C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(PseudoBNE GPRC:$rs1, X0, simm9_lsb0:$imm),
+ (PseudoC_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+let isCompressOnly = true in {
def : CompressPat<(BNE X0, GPRC:$rs1, simm9_lsb0:$imm),
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(PseudoBNE X0, GPRC:$rs1, simm9_lsb0:$imm),
+ (PseudoC_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+}
} // Predicates = [HasStdExtCOrZca]
// Quadrant 2
diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
index 61d605fda3f53a..b8333d0fe7ed6c 100644
--- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -141,8 +141,8 @@ bool RISCVRedundantCopyElimination::optimizeBlock(MachineBasicBlock &MBB) {
return false;
MachineBasicBlock::iterator CondBr = PredMBB->getFirstTerminator();
- assert((CondBr->getOpcode() == RISCV::BEQ ||
- CondBr->getOpcode() == RISCV::BNE) &&
+ assert((CondBr->getOpcode() == RISCV::PseudoBEQ ||
+ CondBr->getOpcode() == RISCV::PseudoBNE) &&
"Unexpected opcode");
assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register");
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir
index 13c4d49b3c4039..03719a5b6120cc 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv32.mir
@@ -16,72 +16,72 @@ body: |
; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
; RV32I-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BEQ [[LW]], [[COPY]], %bb.14
+ ; RV32I-NEXT: PseudoBEQ [[LW]], [[COPY]], %bb.14
; RV32I-NEXT: PseudoBR %bb.1
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.1:
; RV32I-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BNE [[LW1]], [[COPY]], %bb.14
+ ; RV32I-NEXT: PseudoBNE [[LW1]], [[COPY]], %bb.14
; RV32I-NEXT: PseudoBR %bb.2
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.2:
; RV32I-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BLT [[LW2]], [[COPY]], %bb.14
+ ; RV32I-NEXT: PseudoBLT [[LW2]], [[COPY]], %bb.14
; RV32I-NEXT: PseudoBR %bb.3
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.3:
; RV32I-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BGE [[LW3]], [[COPY]], %bb.14
+ ; RV32I-NEXT: PseudoBGE [[LW3]], [[COPY]], %bb.14
; RV32I-NEXT: PseudoBR %bb.4
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.4:
; RV32I-NEXT: [[LW4:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BLTU [[LW4]], [[COPY]], %bb.14
+ ; RV32I-NEXT: PseudoBLTU [[LW4]], [[COPY]], %bb.14
; RV32I-NEXT: PseudoBR %bb.5
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.5:
; RV32I-NEXT: [[LW5:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BGEU [[LW5]], [[COPY]], %bb.14
+ ; RV32I-NEXT: PseudoBGEU [[LW5]], [[COPY]], %bb.14
; RV32I-NEXT: PseudoBR %bb.6
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.6:
; RV32I-NEXT: [[LW6:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BLT [[COPY]], [[LW6]], %bb.14
+ ; RV32I-NEXT: PseudoBLT [[COPY]], [[LW6]], %bb.14
; RV32I-NEXT: PseudoBR %bb.7
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.7:
; RV32I-NEXT: [[LW7:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BGE [[COPY]], [[LW7]], %bb.14
+ ; RV32I-NEXT: PseudoBGE [[COPY]], [[LW7]], %bb.14
; RV32I-NEXT: PseudoBR %bb.8
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.8:
; RV32I-NEXT: [[LW8:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BLTU [[COPY]], [[LW8]], %bb.14
+ ; RV32I-NEXT: PseudoBLTU [[COPY]], [[LW8]], %bb.14
; RV32I-NEXT: PseudoBR %bb.9
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.9:
; RV32I-NEXT: [[LW9:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BGEU [[COPY]], [[LW9]], %bb.14
+ ; RV32I-NEXT: PseudoBGEU [[COPY]], [[LW9]], %bb.14
; RV32I-NEXT: PseudoBR %bb.10
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.10:
; RV32I-NEXT: [[LW10:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
- ; RV32I-NEXT: BNE [[ANDI]], $x0, %bb.14
+ ; RV32I-NEXT: PseudoBNE [[ANDI]], $x0, %bb.14
; RV32I-NEXT: PseudoBR %bb.11
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.11:
; RV32I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000)
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[LW11:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BGE [[LW11]], $x0, %bb.14
+ ; RV32I-NEXT: PseudoBGE [[LW11]], $x0, %bb.14
; RV32I-NEXT: PseudoBR %bb.12
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.12:
; RV32I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000)
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[LW12:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
- ; RV32I-NEXT: BGE $x0, [[LW12]], %bb.14
+ ; RV32I-NEXT: PseudoBGE $x0, [[LW12]], %bb.14
; RV32I-NEXT: PseudoBR %bb.13
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: bb.13:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/brcond-rv64.mir
index de13516e552b12..fd48569f6f1c9e 100644
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/87834
More information about the llvm-commits
mailing list