[llvm] 4abb722 - [RISCV] Add tests for opportunities to reassociate to form more shXadd instructions. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 5 12:51:17 PDT 2024
Author: Craig Topper
Date: 2024-04-05T12:50:48-07:00
New Revision: 4abb722ffa7fcf809faa4a479fdf2f78c685b351
URL: https://github.com/llvm/llvm-project/commit/4abb722ffa7fcf809faa4a479fdf2f78c685b351
DIFF: https://github.com/llvm/llvm-project/commit/4abb722ffa7fcf809faa4a479fdf2f78c685b351.diff
LOG: [RISCV] Add tests for opportunities to reassociate to form more shXadd instructions. NFC
These tests consist of patterns like (sh3add Z, (add X, (slli Y, 6)))
that can be reassociated to form (sh3add (sh3add Y, Z), X).
Added:
Modified:
llvm/test/CodeGen/RISCV/rv64zba.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index c81c6aeaab890c..7e32253c8653f1 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -2036,3 +2036,364 @@ define i64 @pack_i64_disjoint_2(i32 signext %a, i64 %b) nounwind {
%or = or disjoint i64 %b, %zexta
ret i64 %or
}
+
+define i8 @array_index_sh1_sh0(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh1_sh0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 1
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: lbu a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh1_sh0:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sh1add a0, a1, a0
+; RV64ZBA-NEXT: add a0, a0, a2
+; RV64ZBA-NEXT: lbu a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [2 x i8], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i8, ptr %a, align 1
+ ret i8 %b
+}
+
+define i16 @array_index_sh1_sh1(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh1_sh1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 1
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lh a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh1_sh1:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sh2add a0, a1, a0
+; RV64ZBA-NEXT: sh1add a0, a2, a0
+; RV64ZBA-NEXT: lh a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [2 x i16], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i16, ptr %a, align 2
+ ret i16 %b
+}
+
+define i32 @array_index_sh1_sh2(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh1_sh2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 3
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 2
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh1_sh2:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sh3add a0, a1, a0
+; RV64ZBA-NEXT: sh2add a0, a2, a0
+; RV64ZBA-NEXT: lw a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [2 x i32], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i32, ptr %a, align 4
+ ret i32 %b
+}
+
+define i64 @array_index_sh1_sh3(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh1_sh3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 3
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: ld a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh1_sh3:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 4
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh3add a0, a2, a0
+; RV64ZBA-NEXT: ld a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [2 x i64], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i64, ptr %a, align 8
+ ret i64 %b
+}
+
+define i8 @array_index_sh2_sh0(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh2_sh0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 2
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: lbu a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh2_sh0:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sh2add a0, a1, a0
+; RV64ZBA-NEXT: add a0, a0, a2
+; RV64ZBA-NEXT: lbu a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [4 x i8], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i8, ptr %a, align 1
+ ret i8 %b
+}
+
+define i16 @array_index_sh2_sh1(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh2_sh1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 3
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 1
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lh a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh2_sh1:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sh3add a0, a1, a0
+; RV64ZBA-NEXT: sh1add a0, a2, a0
+; RV64ZBA-NEXT: lh a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [4 x i16], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i16, ptr %a, align 2
+ ret i16 %b
+}
+
+define i32 @array_index_sh2_sh2(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh2_sh2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 2
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh2_sh2:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 4
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh2add a0, a2, a0
+; RV64ZBA-NEXT: lw a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [4 x i32], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i32, ptr %a, align 4
+ ret i32 %b
+}
+
+define i64 @array_index_sh2_sh3(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh2_sh3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 5
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 3
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: ld a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh2_sh3:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 5
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh3add a0, a2, a0
+; RV64ZBA-NEXT: ld a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [4 x i64], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i64, ptr %a, align 8
+ ret i64 %b
+}
+
+define i8 @array_index_sh3_sh0(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh3_sh0:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 3
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: lbu a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh3_sh0:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sh3add a0, a1, a0
+; RV64ZBA-NEXT: add a0, a0, a2
+; RV64ZBA-NEXT: lbu a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [8 x i8], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i8, ptr %a, align 1
+ ret i8 %b
+}
+
+define i16 @array_index_sh3_sh1(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh3_sh1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 4
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 1
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lh a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh3_sh1:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 4
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh1add a0, a2, a0
+; RV64ZBA-NEXT: lh a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [8 x i16], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i16, ptr %a, align 2
+ ret i16 %b
+}
+
+define i32 @array_index_sh3_sh2(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh3_sh2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 5
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 2
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh3_sh2:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 5
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh2add a0, a2, a0
+; RV64ZBA-NEXT: lw a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [8 x i32], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i32, ptr %a, align 4
+ ret i32 %b
+}
+
+define i64 @array_index_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh3_sh3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 6
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 3
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: ld a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh3_sh3:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 6
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh3add a0, a2, a0
+; RV64ZBA-NEXT: ld a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [8 x i64], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i64, ptr %a, align 8
+ ret i64 %b
+}
+
+; Similar to above, but with a lshr on one of the indices. This requires
+; special handling during isel to form a shift pair.
+define i64 @array_index_lshr_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_lshr_sh3_sh3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a1, a1, 58
+; RV64I-NEXT: slli a1, a1, 6
+; RV64I-NEXT: slli a2, a2, 3
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ld a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_lshr_sh3_sh3:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: srli a1, a1, 58
+; RV64ZBA-NEXT: slli a1, a1, 6
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh3add a0, a2, a0
+; RV64ZBA-NEXT: ld a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %shr = lshr i64 %idx1, 58
+ %a = getelementptr inbounds [8 x i64], ptr %p, i64 %shr, i64 %idx2
+ %b = load i64, ptr %a, align 8
+ ret i64 %b
+}
+
+define i8 @array_index_sh4_sh0(ptr %p, i64 %idx1, i64 %idx2) {
+; CHECK-LABEL: array_index_sh4_sh0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a0, a0, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: lbu a0, 0(a0)
+; CHECK-NEXT: ret
+ %a = getelementptr inbounds [16 x i8], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i8, ptr %a, align 1
+ ret i8 %b
+}
+
+define i16 @array_index_sh4_sh1(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh4_sh1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 5
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 1
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lh a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh4_sh1:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 5
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh1add a0, a2, a0
+; RV64ZBA-NEXT: lh a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [16 x i16], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i16, ptr %a, align 2
+ ret i16 %b
+}
+
+define i32 @array_index_sh4_sh2(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh4_sh2:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 6
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 2
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh4_sh2:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 6
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh2add a0, a2, a0
+; RV64ZBA-NEXT: lw a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [16 x i32], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i32, ptr %a, align 4
+ ret i32 %b
+}
+
+define i64 @array_index_sh4_sh3(ptr %p, i64 %idx1, i64 %idx2) {
+; RV64I-LABEL: array_index_sh4_sh3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a1, a1, 7
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: slli a2, a2, 3
+; RV64I-NEXT: add a0, a0, a2
+; RV64I-NEXT: ld a0, 0(a0)
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: array_index_sh4_sh3:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a1, a1, 7
+; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: sh3add a0, a2, a0
+; RV64ZBA-NEXT: ld a0, 0(a0)
+; RV64ZBA-NEXT: ret
+ %a = getelementptr inbounds [16 x i64], ptr %p, i64 %idx1, i64 %idx2
+ %b = load i64, ptr %a, align 8
+ ret i64 %b
+}
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