[llvm] e7e7827 - [RISCV] Remove uses of sed from compress-opt-branch.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 5 12:44:21 PDT 2024
Author: Craig Topper
Date: 2024-04-05T12:35:46-07:00
New Revision: e7e78274a66df59ce3f2fa2bfd8a554e637ee0b6
URL: https://github.com/llvm/llvm-project/commit/e7e78274a66df59ce3f2fa2bfd8a554e637ee0b6
DIFF: https://github.com/llvm/llvm-project/commit/e7e78274a66df59ce3f2fa2bfd8a554e637ee0b6.diff
LOG: [RISCV] Remove uses of sed from compress-opt-branch.ll. NFC
sed was being used to use the same test functions with eq/ne branch
condition.
This commit duplicates the test functions so that we have a version
with each condition. This allows us to remove 2 RUN lines.
I plan to add a Zca testing to this file which now requires 1 new
RUN line instead of 2.
Added:
Modified:
llvm/test/CodeGen/RISCV/compress-opt-branch.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll
index 354f180b45a990..44eaf4bdc207e7 100644
--- a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll
+++ b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll
@@ -3,45 +3,50 @@
; The optimization should appear only with +c, otherwise default isel should be
; choosen.
;
-; RUN: cat %s | sed 's/CMPCOND/eq/g' | sed 's/RESBRNORMAL/bne/g' | \
-; RUN: sed 's/RESBROPT/c.bnez/g' > %t.compress_eq
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
-; RUN: -disable-block-placement < %t.compress_eq \
+; RUN: -disable-block-placement < %s \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %t.compress_eq
+; RUN: | FileCheck -check-prefix=RV32IFDC %s
;
-; RUN: cat %s | sed -e 's/CMPCOND/eq/g' | sed -e 's/RESBRNORMAL/bne/g'\
-; RUN: | sed -e 's/RESBROPT/c.bnez/g' > %t.nocompr_eq
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
-; RUN: -disable-block-placement < %t.nocompr_eq \
+; RUN: -disable-block-placement < %s \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFD %t.nocompr_eq
-;
-; RUN: cat %s | sed 's/CMPCOND/ne/g' | sed 's/RESBRNORMAL/beq/g' | \
-; RUN: sed 's/RESBROPT/c.beqz/g' > %t.compress_neq
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
-; RUN: -disable-block-placement < %t.compress_neq \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFDC %t.compress_neq
-;
-; RUN: cat %s | sed -e 's/CMPCOND/ne/g' | sed -e 's/RESBRNORMAL/beq/g'\
-; RUN: | sed -e 's/RESBROPT/c.beqz/g' > %t.nocompr_neq
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
-; RUN: -disable-block-placement < %t.nocompr_neq \
-; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
-; RUN: | FileCheck -check-prefix=RV32IFD %t.nocompr_neq
+; RUN: | FileCheck -check-prefix=RV32IFD %s
+
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_pos_eq>:
+; RV32IFDC: c.li [[REG:.*]], 0x14
+; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_pos_eq>:
+; RV32IFD: addi [[REG:.*]], zero, 0x14
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_pos_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, 20
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <f_small_pos>:
+; RV32IFDC-LABEL: <f_small_pos_ne>:
; RV32IFDC: c.li [[REG:.*]], 0x14
-; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_small_pos>:
+; RV32IFD-LABEL: <f_small_pos_ne>:
; RV32IFD: addi [[REG:.*]], zero, 0x14
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_small_pos(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, 20
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_pos_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, 20
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -56,15 +61,61 @@ if.end:
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <f_small_neg>:
+; RV32IFDC-LABEL: <f_small_neg_eq>:
; RV32IFDC: c.li [[REG:.*]], -0x14
-; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_small_neg>:
+; RV32IFD-LABEL: <f_small_neg_eq>:
; RV32IFD: addi [[REG:.*]], zero, -0x14
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_small_neg(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, -20
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_neg_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, -20
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_neg_ne>:
+; RV32IFDC: c.li [[REG:.*]], -0x14
+; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_neg_ne>:
+; RV32IFD: addi [[REG:.*]], zero, -0x14
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_neg_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, -20
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_edge_pos_eq>:
+; RV32IFDC: c.li [[REG:.*]], 0x1f
+; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_edge_pos_eq>:
+; RV32IFD: addi [[REG:.*]], zero, 0x1f
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_pos_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, 31
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -79,15 +130,38 @@ if.end:
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <f_small_edge_pos>:
+; RV32IFDC-LABEL: <f_small_edge_pos_ne>:
; RV32IFDC: c.li [[REG:.*]], 0x1f
-; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_small_edge_pos>:
+; RV32IFD-LABEL: <f_small_edge_pos_ne>:
; RV32IFD: addi [[REG:.*]], zero, 0x1f
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_small_edge_pos(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, 31
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_pos_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, 31
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is small and fit in 6 bit (compress imm)
+; RV32IFDC-LABEL: <f_small_edge_neg_eq>:
+; RV32IFDC: c.li [[REG:.*]], -0x20
+; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_small_edge_neg_eq>:
+; RV32IFD: addi [[REG:.*]], zero, -0x20
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_neg_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, -32
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -102,15 +176,15 @@ if.end:
}
; constant is small and fit in 6 bit (compress imm)
-; RV32IFDC-LABEL: <f_small_edge_neg>:
+; RV32IFDC-LABEL: <f_small_edge_neg_ne>:
; RV32IFDC: c.li [[REG:.*]], -0x20
-; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_small_edge_neg>:
+; RV32IFD-LABEL: <f_small_edge_neg_ne>:
; RV32IFD: addi [[REG:.*]], zero, -0x20
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_small_edge_neg(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, -32
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_small_edge_neg_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, -32
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -126,15 +200,63 @@ if.end:
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <f_medium_ledge_pos>:
+; RV32IFDC-LABEL: <f_medium_ledge_pos_eq>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x20
-; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_medium_ledge_pos>:
+; RV32IFD-LABEL: <f_medium_ledge_pos_eq>:
; RV32IFD: addi [[REG:.*]], zero, 0x20
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_medium_ledge_pos(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, 32
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_pos_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, 32
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_ledge_pos_ne>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x20
+; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_ledge_pos_ne>:
+; RV32IFD: addi [[REG:.*]], zero, 0x20
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_pos_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, 32
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_ledge_neg_eq>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x21
+; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_ledge_neg_eq>:
+; RV32IFD: addi [[REG:.*]], zero, -0x21
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_neg_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, -33
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -150,15 +272,15 @@ if.end:
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <f_medium_ledge_neg>:
+; RV32IFDC-LABEL: <f_medium_ledge_neg_ne>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x21
-; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_medium_ledge_neg>:
+; RV32IFD-LABEL: <f_medium_ledge_neg_ne>:
; RV32IFD: addi [[REG:.*]], zero, -0x21
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_medium_ledge_neg(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, -33
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_ledge_neg_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, -33
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -174,15 +296,15 @@ if.end:
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <f_medium_pos>:
+; RV32IFDC-LABEL: <f_medium_pos_eq>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x3f
-; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_medium_pos>:
+; RV32IFD-LABEL: <f_medium_pos_eq>:
; RV32IFD: addi [[REG:.*]], zero, 0x3f
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_medium_pos(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, 63
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_pos_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, 63
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -198,15 +320,39 @@ if.end:
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <f_medium_neg>:
+; RV32IFDC-LABEL: <f_medium_pos_ne>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x3f
+; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_pos_ne>:
+; RV32IFD: addi [[REG:.*]], zero, 0x3f
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_pos_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, 63
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_neg_eq>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x3f
-; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_medium_neg>:
+; RV32IFD-LABEL: <f_medium_neg_eq>:
; RV32IFD: addi [[REG:.*]], zero, -0x3f
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_medium_neg(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, -63
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_neg_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, -63
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -222,15 +368,87 @@ if.end:
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
-; RV32IFDC-LABEL: <f_medium_bedge_pos>:
+; RV32IFDC-LABEL: <f_medium_neg_ne>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x3f
+; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_neg_ne>:
+; RV32IFD: addi [[REG:.*]], zero, -0x3f
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_neg_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, -63
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_bedge_pos_eq>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x7ff
-; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_medium_bedge_pos>:
+; RV32IFD-LABEL: <f_medium_bedge_pos_eq>:
; RV32IFD: addi [[REG:.*]], zero, 0x7ff
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_medium_bedge_pos(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, 2047
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_pos_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, 2047
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm)
+; RV32IFDC-LABEL: <f_medium_bedge_pos_ne>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x7ff
+; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_bedge_pos_ne>:
+; RV32IFD: addi [[REG:.*]], zero, 0x7ff
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_pos_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, 2047
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is medium and not fit in 6 bit (compress imm),
+; but fit in 12 bit (imm), negative value fit in 12 bit too.
+; RV32IFDC-LABEL: <f_medium_bedge_neg_eq>:
+; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x7ff
+; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_medium_bedge_neg_eq>:
+; RV32IFD: addi [[REG:.*]], zero, -0x7ff
+; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_neg_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, -2047
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -246,15 +464,15 @@ if.end:
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm), negative value fit in 12 bit too.
-; RV32IFDC-LABEL: <f_medium_bedge_neg>:
+; RV32IFDC-LABEL: <f_medium_bedge_neg_ne>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x7ff
-; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
+; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_medium_bedge_neg>:
+; RV32IFD-LABEL: <f_medium_bedge_neg_ne>:
; RV32IFD: addi [[REG:.*]], zero, -0x7ff
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
-define i32 @f_medium_bedge_neg(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, -2047
+; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+define i32 @f_medium_bedge_neg_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, -2047
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -269,17 +487,67 @@ if.end:
}
; constant is big and do not fit in 12 bit (imm), fit in i32
-; RV32IFDC-LABEL: <f_big_ledge_pos>:
+; RV32IFDC-LABEL: <f_big_ledge_pos_eq>:
; RV32IFDC: c.li [[REG:.*]], 0x1
; RV32IFDC: c.slli [[REG]], 0xb
-; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_big_ledge_pos>:
+; RV32IFD-LABEL: <f_big_ledge_pos_eq>:
; RV32IFD: addi [[REG1:.*]], zero, 0x1
; RV32IFD: slli [[REG2:.*]], [[REG1]], 0xb
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]]
-define i32 @f_big_ledge_pos(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, 2048
+; RV32IFD: bne [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]]
+define i32 @f_big_ledge_pos_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, 2048
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is big and do not fit in 12 bit (imm), fit in i32
+; RV32IFDC-LABEL: <f_big_ledge_pos_ne>:
+; RV32IFDC: c.li [[REG:.*]], 0x1
+; RV32IFDC: c.slli [[REG]], 0xb
+; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_big_ledge_pos_ne>:
+; RV32IFD: addi [[REG1:.*]], zero, 0x1
+; RV32IFD: slli [[REG2:.*]], [[REG1]], 0xb
+; RV32IFD: beq [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]]
+define i32 @f_big_ledge_pos_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, 2048
+ br i1 %cmp, label %if.then, label %if.else
+if.then:
+ %call = shl i32 %in0, 1
+ br label %if.end
+if.else:
+ %call2 = add i32 %in0, 42
+ br label %if.end
+
+if.end:
+ %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ]
+ ret i32 %toRet
+}
+
+; constant is big and do not fit in 12 bit (imm), fit in i32
+; RV32IFDC-LABEL: <f_big_ledge_neg_eq>:
+; RV32IFDC: c.lui [[REG1:.*]], 0xfffff
+; RV32IFDC: addi [[REG2:.*]], [[REG1]], 0x7ff
+; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; --- no compress extension
+; RV32IFD-LABEL: <f_big_ledge_neg_eq>:
+; RV32IFD: lui [[REG1:.*]], 0xfffff
+; RV32IFD: addi [[REG2:.*]], [[REG1]], 0x7ff
+; RV32IFD: bne [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]]
+define i32 @f_big_ledge_neg_eq(i32 %in0) minsize {
+ %cmp = icmp eq i32 %in0, -2049
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
@@ -294,17 +562,17 @@ if.end:
}
; constant is big and do not fit in 12 bit (imm), fit in i32
-; RV32IFDC-LABEL: <f_big_ledge_neg>:
+; RV32IFDC-LABEL: <f_big_ledge_neg_ne>:
; RV32IFDC: c.lui [[REG1:.*]], 0xfffff
; RV32IFDC: addi [[REG2:.*]], [[REG1]], 0x7ff
-; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
+; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
-; RV32IFD-LABEL: <f_big_ledge_neg>:
+; RV32IFD-LABEL: <f_big_ledge_neg_ne>:
; RV32IFD: lui [[REG1:.*]], 0xfffff
; RV32IFD: addi [[REG2:.*]], [[REG1]], 0x7ff
-; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]]
-define i32 @f_big_ledge_neg(i32 %in0) minsize {
- %cmp = icmp CMPCOND i32 %in0, -2049
+; RV32IFD: beq [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]]
+define i32 @f_big_ledge_neg_ne(i32 %in0) minsize {
+ %cmp = icmp ne i32 %in0, -2049
br i1 %cmp, label %if.then, label %if.else
if.then:
%call = shl i32 %in0, 1
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