[llvm] [AArch64] Remove copy in SVE/SME predicate spill and fill (PR #81716)

[Sam Tebbs via llvm-commits]

================
@@ -4813,24 +4813,22 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   case 2:
     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
       Opc = AArch64::STRHui;
-    else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
-      assert(Subtarget.hasSVEorSME() &&
-             "Unexpected register store without SVE store instructions");
-      Opc = AArch64::STR_PXI;
-      StackID = TargetStackID::ScalableVector;
-    } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
-      assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
-             "Unexpected register store without SVE2p1 or SME2");
-      if (SrcReg.isVirtual()) {
-        auto NewSrcReg =
-            MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
-        BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg)
-            .addReg(SrcReg);
-        SrcReg = NewSrcReg;
-      } else
-        SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
-      Opc = AArch64::STR_PXI;
-      StackID = TargetStackID::ScalableVector;
+    else {
+      bool IsPPR = AArch64::PPRRegClass.hasSubClassEq(RC);
+      bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
+      if (IsPPR || IsPNR) {
+        assert((!IsPPR || Subtarget.hasSVEorSME()) &&
+               "Unexpected register store without SVE store instructions");
+        assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
+               "Unexpected register store without SVE2p1 or SME2");
+        Opc = AArch64::STR_PXI;
+        StackID = TargetStackID::ScalableVector;
+        if (SrcReg.isVirtual())
+          MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::PPRRegClass);
+        else if (IsPNR)
+          // Normalise to PPR
+          SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
+      }
----------------
SamTebbs33 wrote:

You're right! Thanks. I've kept the `IsPNR` and `IsPPR` variables though so we can emit the right assertions.

https://github.com/llvm/llvm-project/pull/81716