[llvm] [AMDGPU] Fix implicit $vcc operands after parsing MIR (PR #87781)

[Jay Foad via llvm-commits]

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@@ -586,7 +586,7 @@ name: dpp_reg_sequence_both_combined
 tracksRegLiveness: true
 body: |
   bb.0:
-    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo
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jayfoad wrote:

In wave32 mode we reserve $vcc, so implicit uses of $vcc did not need a corresponding def. Now these uses are being converted to $vcc_lo, which is not reserved, so we do need to supply a def.

https://github.com/llvm/llvm-project/pull/87781