[lld] [ELF, test] Add test for R_AARCH64_* implicit addends (PR #87733)
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 4 19:07:34 PDT 2024
https://github.com/MaskRay created https://github.com/llvm/llvm-project/pull/87733
See #87328 for the armasm context.
>From c9614ee62b12b061d1e93f0b0b70cb27d7312626 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Thu, 4 Apr 2024 19:07:23 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
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Created using spr 1.3.5-bogner
---
.../ELF/aarch64-reloc-implicit-addend.test | 86 +++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 lld/test/ELF/aarch64-reloc-implicit-addend.test
diff --git a/lld/test/ELF/aarch64-reloc-implicit-addend.test b/lld/test/ELF/aarch64-reloc-implicit-addend.test
new file mode 100644
index 00000000000000..15f42c4d87b577
--- /dev/null
+++ b/lld/test/ELF/aarch64-reloc-implicit-addend.test
@@ -0,0 +1,86 @@
+## Test certain REL relocation types generated by legacy armasm.
+# RUN: yaml2obj %s -o %t.o
+# RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s
+
+# CHECK-COUNT-17: internal linker error: cannot read addend
+
+---
+!ELF
+FileHeader:
+ Class: ELFCLASS64
+ Data: ELFDATA2LSB
+ Type: ET_REL
+ Machine: EM_AARCH64
+Sections:
+ - Name: .abs
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC ]
+ Content: fffffefffffffdfffffffffffffffcffffffffffffff
+ - Name: .rel.abs
+ Type: SHT_REL
+ Link: .symtab
+ Info: .abs
+ Relocations:
+ - {Offset: 0, Symbol: abs, Type: R_AARCH64_ABS16}
+ - {Offset: 2, Symbol: abs, Type: R_AARCH64_ABS32}
+ - {Offset: 6, Symbol: abs, Type: R_AARCH64_ABS64}
+ - {Offset: 14, Symbol: abs, Type: R_AARCH64_ADD_ABS_LO12_NC}
+
+ - Name: .uabs
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC ]
+ AddressAlign: 4
+ Content: 00ffffff00ffffff00ffffff00ffffff00ffffff00ffffff
+ - Name: .rel.uabs
+ Type: SHT_REL
+ Link: .symtab
+ Info: .uabs
+ Relocations:
+ - {Offset: 0, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G0}
+ - {Offset: 4, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G0_NC}
+ - {Offset: 8, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G1}
+ - {Offset: 12, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G1_NC}
+ - {Offset: 16, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G2}
+ - {Offset: 20, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G2_NC}
+
+ - Name: .prel
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC ]
+ AddressAlign: 4
+ Content: 00ffffff00ffffff00ffffff00ffffff00ffffff00ffffff
+ - Name: .rel.prel
+ Type: SHT_REL
+ Link: .symtab
+ Info: .prel
+ Relocations:
+ - {Offset: 0, Symbol: .prel, Type: R_AARCH64_PREL64}
+ - {Offset: 4, Symbol: .prel, Type: R_AARCH64_PREL32}
+ - {Offset: 8, Symbol: .prel, Type: R_AARCH64_PREL16}
+ - {Offset: 12, Symbol: .prel, Type: R_AARCH64_LD_PREL_LO19}
+ - {Offset: 16, Symbol: .prel, Type: R_AARCH64_ADR_PREL_PG_HI21}
+ - {Offset: 20, Symbol: .prel, Type: R_AARCH64_ADR_PREL_PG_HI21_NC}
+
+ - Name: .branch
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC ]
+ AddressAlign: 4
+ Content: f0fffffff0fffffff0fffffff0ffffff
+ - Name: .rel.branch
+ Type: SHT_REL
+ Link: .symtab
+ Info: .branch
+ Relocations:
+ - {Offset: 0, Symbol: .branch, Type: R_AARCH64_TSTBR14}
+ - {Offset: 4, Symbol: .branch, Type: R_AARCH64_CONDBR19}
+ - {Offset: 8, Symbol: .branch, Type: R_AARCH64_CALL26}
+ - {Offset: 12, Symbol: .branch, Type: R_AARCH64_JUMP26}
+
+Symbols:
+ - Name: .branch
+ Section: .branch
+ - Name: .prel
+ Section: .prel
+ - Name: abs
+ Index: SHN_ABS
+ Value: 42
+ Binding: STB_GLOBAL
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