[llvm] [RISCV] Add a MIR pass to reassociate shXadd, add, and slli to form more shXadd. (PR #87544)

[Philip Reames via llvm-commits]

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@@ -2036,3 +2035,357 @@ define i64 @pack_i64_disjoint_2(i32 signext %a, i64 %b) nounwind {
   %or = or disjoint i64 %b, %zexta
   ret i64 %or
 }
+
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preames wrote:

Can you precommit your tests and rebase please?

https://github.com/llvm/llvm-project/pull/87544