[llvm] [SelectionDAG] Fix and improve TargetLowering::SimplifySetCC (PR #87646)

[Björn Pettersson via llvm-commits]

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@@ -27,7 +27,9 @@ define i1 @test_129_15_0(ptr %y) {
 ;
 ; CHECK-BE-LABEL: test_129_15_0:
 ; CHECK-BE:       @ %bb.0:
-; CHECK-BE-NEXT:    ldrh r0, [r0, #14]
+; CHECK-BE-NEXT:    ldr r1, [r0, #12]
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bjope wrote:

This is not a regression. It is supposed to be fixing a miscompile.

The 15bits masked out with the AND is at [r0, #15]  and [r0, #16]. I think the optimization to narrow to a 16-bit load is blocked due to loading 16 bits starting at [r0, #15] would be an unaligned load.

https://github.com/llvm/llvm-project/pull/87646