[llvm] 4e0b8ea - [RISCV] Add tests for vwsll for extends > .vf2. NFC
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 4 03:43:27 PDT 2024
Author: Luke Lau
Date: 2024-04-04T18:43:15+08:00
New Revision: 4e0b8eae4cb4328f98e6b748c31050a704d378f6
URL: https://github.com/llvm/llvm-project/commit/4e0b8eae4cb4328f98e6b748c31050a704d378f6
DIFF: https://github.com/llvm/llvm-project/commit/4e0b8eae4cb4328f98e6b748c31050a704d378f6.diff
LOG: [RISCV] Add tests for vwsll for extends > .vf2. NFC
These cannot be picked up by TableGen patterns alone and need to be handled
by combineBinOp_VLToVWBinOp_VL
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
index 770bb566c764cd..082de2e7bf77bf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
@@ -627,3 +627,259 @@ define <vscale x 8 x i16> @vwsll_vi_nxv8i16(<vscale x 8 x i8> %a) {
%z = shl <vscale x 8 x i16> %x, splat (i16 2)
ret <vscale x 8 x i16> %z
}
+
+; ==============================================================================
+; i8 -> i64
+; ==============================================================================
+
+define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
+; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vsext.vf8 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = sext <vscale x 2 x i8> %b to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
+; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vzext.vf8 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64_nxv2i8(<vscale x 2 x i8> %a, i64 %b) {
+; CHECK-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vsll.vx v8, v10, a0
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0
+; CHECK-ZVBB-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %splat
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i32 %b) {
+; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vsext.vf2 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
+; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i32 %b) {
+; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vzext.vf2 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
+; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i16 %b) {
+; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vsext.vf4 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
+; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vsext.vf4 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i16 %b) {
+; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vzext.vf4 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
+; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i8 %b) {
+; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vsext.vf8 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
+; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i8 %b) {
+; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv.v.x v9, a0
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vzext.vf8 v12, v9
+; CHECK-NEXT: vsll.vv v8, v10, v12
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
+; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
+; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
+; CHECK-ZVBB-NEXT: ret
+ %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 2 x i64> @vwsll_vi_nxv2i64_nxv2i8(<vscale x 2 x i8> %a) {
+; CHECK-LABEL: vwsll_vi_nxv2i64_nxv2i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-NEXT: vzext.vf8 v10, v8
+; CHECK-NEXT: vsll.vi v8, v10, 2
+; CHECK-NEXT: ret
+;
+; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
+; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2
+; CHECK-ZVBB-NEXT: ret
+ %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, splat (i64 2)
+ ret <vscale x 2 x i64> %z
+}
More information about the llvm-commits
mailing list