[llvm] a853d79 - [RISCV][GISel] Don't check for FP uses of of IMPLICIT_DEF if the type is vector. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 3 18:53:21 PDT 2024
Author: Craig Topper
Date: 2024-04-03T18:49:55-07:00
New Revision: a853d79963c6ac09154817690a8c317157345876
URL: https://github.com/llvm/llvm-project/commit/a853d79963c6ac09154817690a8c317157345876
DIFF: https://github.com/llvm/llvm-project/commit/a853d79963c6ac09154817690a8c317157345876.diff
LOG: [RISCV][GISel] Don't check for FP uses of of IMPLICIT_DEF if the type is vector. NFC
If the type is vector, we can immediately know to use vector mapping.
Previously we searched for FP uses, but then replaced it if the type
was vector.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 4f34514c2cfe18..8534024b6002b6 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -341,18 +341,17 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_IMPLICIT_DEF: {
Register Dst = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(Dst);
- uint64_t DstMinSize = DstTy.getSizeInBits().getKnownMinValue();
+ unsigned DstMinSize = DstTy.getSizeInBits().getKnownMinValue();
auto Mapping = GPRValueMapping;
// FIXME: May need to do a better job determining when to use FPRB.
// For example, the look through COPY case:
// %0:_(s32) = G_IMPLICIT_DEF
// %1:_(s32) = COPY %0
// $f10_d = COPY %1(s32)
- if (anyUseOnlyUseFP(Dst, MRI, TRI))
- Mapping = getFPValueMapping(DstMinSize);
-
if (DstTy.isVector())
Mapping = getVRBValueMapping(DstMinSize);
+ else if (anyUseOnlyUseFP(Dst, MRI, TRI))
+ Mapping = getFPValueMapping(DstMinSize);
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, Mapping,
NumOperands);
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