[llvm] 3b19cd7 - [RISCV] Slightly simplify RVVArgDispatcher::constructArgInfos. NFC (#87308)

[via llvm-commits]

Author: Craig Topper
Date: 2024-04-02T18:34:03-07:00
New Revision: 3b19cd7f80d8464d5f1bd8b2a0adf925d10556c4

URL: https://github.com/llvm/llvm-project/commit/3b19cd7f80d8464d5f1bd8b2a0adf925d10556c4
DIFF: https://github.com/llvm/llvm-project/commit/3b19cd7f80d8464d5f1bd8b2a0adf925d10556c4.diff

LOG: [RISCV] Slightly simplify RVVArgDispatcher::constructArgInfos. NFC (#87308)

Use a single insert for the non-mask case instead of a push_back
followed by an insert that may contain 0 registers.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ee83f9da4934b8..279d8a435a04ca 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21115,12 +21115,10 @@ void RVVArgDispatcher::constructArgInfos(ArrayRef<Type *> TypeList) {
             RegisterVT.getVectorElementType() == MVT::i1) {
           RVVArgInfos.push_back({1, RegisterVT, true});
           FirstVMaskAssigned = true;
-        } else {
-          RVVArgInfos.push_back({1, RegisterVT, false});
+          --NumRegs;
         }
 
-        RVVArgInfos.insert(RVVArgInfos.end(), --NumRegs,
-                           {1, RegisterVT, false});
+        RVVArgInfos.insert(RVVArgInfos.end(), NumRegs, {1, RegisterVT, false});
       }
     }
   }