[llvm] [RISCV][GISEL] Regbankselect and instructionselect for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type (PR #87363)

[Craig Topper via llvm-commits]

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@@ -366,6 +372,19 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   SmallVector<const ValueMapping *, 4> OpdsMapping(NumOperands);
 
   switch (Opc) {
+  case TargetOpcode::G_ANYEXT:
+  case TargetOpcode::G_SEXT:
+  case TargetOpcode::G_ZEXT: {
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topperc wrote:

As I said on the G_ICMP patch, we should make the default case understand vectors.

https://github.com/llvm/llvm-project/pull/87363