[llvm] [RISCV][GISEL] Regbank select and instruction select for scalable vector G_ICMP (PR #87362)

[Craig Topper via llvm-commits]

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@@ -487,6 +487,19 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     OpdsMapping[1] = GPRValueMapping;
     break;
   }
+  case TargetOpcode::G_ICMP: {
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {
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topperc wrote:

Can you just add vector support to the default case?

https://github.com/llvm/llvm-project/pull/87362