[llvm] [AArch64] Remove copy in SVE/SME predicate spill and fill (PR #81716)

[Sam Tebbs via llvm-commits]

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@@ -1770,6 +1788,15 @@ class AArch64Operand : public MCParsedAsmOperand {
     Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
   }
 
+  void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    unsigned Reg = getReg();
+    // Normalise to PPR
+    if (Reg >= AArch64::PN0)
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SamTebbs33 wrote:

Done

https://github.com/llvm/llvm-project/pull/81716