[llvm] [ARM][AArch64] Fix extremely probable documentation error in A57 (PR #87354)

[via llvm-commits]

https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/87354

>From 8b5dc3ab52fac6e852a11266b7ea1206875e6c48 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Mon, 1 Apr 2024 21:04:22 -0400
Subject: [PATCH] [ARM][AArch64] Fix extremely probable documentation error in
 A57

It makes no sense that shift operation uses the I0/I1 anyway
as opposed to M, especially when the more complex instruction
uses the simpler pipeline. We should assume both use M pipeline,
and a note should be made that this is a deviation from the doc
because of its high likelihood of being an error.
---
 llvm/lib/Target/ARM/ARMScheduleA57.td | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 3baac6b233c458..da59097b0de233 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -179,15 +179,21 @@ class A57BranchForm<SchedWriteRes non_br> :
   BranchWriteRes<2, 1, [A57UnitB], [1], non_br>;
 
 // shift by register, conditional or unconditional
+//
 // TODO: according to the doc, conditional uses I0/I1, unconditional uses M
 // Why more complex instruction uses more simple pipeline?
-// May be an error in doc.
+// It makes no sense that a shift operation uses the I0/I1 anyway as opposed to M,
+// and this is the only operation to do so, so it makes logical sense that both
+// actually use the M pipeline.
+//
+// For now, assume the doc makes an error in this regard.
+
 def A57WriteALUsr : SchedWriteVariant<[
-  SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1I>>]>,
+  SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>,
   SchedVar<NoSchedPred,      [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>
 ]>;
 def A57WriteALUSsr : SchedWriteVariant<[
-  SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1I>>]>,
+  SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>,
   SchedVar<NoSchedPred,      [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>
 ]>;
 def A57ReadALUsr : SchedReadVariant<[