[llvm] [DAGCombiner][RISCV] Handle truncating splats in isNeutralConstant (PR #87338)

[Luke Lau via llvm-commits]

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@@ -11549,30 +11549,31 @@ bool llvm::isNeutralConstant(unsigned Opcode, SDNodeFlags Flags, SDValue V,
                              unsigned OperandNo) {
   // NOTE: The cases should match with IR's ConstantExpr::getBinOpIdentity().
   // TODO: Target-specific opcodes could be added.
-  if (auto *Const = isConstOrConstSplat(V)) {
+  if (auto *ConstV = isConstOrConstSplat(V, false, true)) {
+    APInt Const = ConstV->getAPIntValue().trunc(V.getScalarValueSizeInBits());
----------------
lukel97 wrote:

I tried but I couldn't think of how to. We need to create a splat_vector that implicitly truncates, but if you create it via a regular splat in IR it will arrive in SelectionDAG with a matching type. 

It will eventually get type legalized to a truncating splat_vector but by then the fold will have already happened in the first round of DAG combine:

```
Initial selection DAG: %bb.0 'add:'
SelectionDAG has 19 nodes:
  t0: ch,glue = EntryToken
  t4: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %1
  t10: nxv2i32 = insert_vector_elt undef:nxv2i32, Constant:i32<1>, Constant:i64<0>
      t2: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %0
        t6: nxv2i1,ch = CopyFromReg t0, Register:nxv2i1 %2
        t11: nxv2i32 = splat_vector Constant:i32<1>
        t13: nxv2i32 = splat_vector Constant:i32<0>
      t14: nxv2i32 = vselect t6, t11, t13
    t15: nxv2i32 = add t2, t14
  t17: ch,glue = CopyToReg t0, Register:nxv2i32 $v8, t15
  t18: ch = RISCVISD::RET_GLUE t17, Register:nxv2i32 $v8, t17:1



Optimized lowered selection DAG: %bb.0 'add:'
SelectionDAG has 13 nodes:
  t0: ch,glue = EntryToken
      t6: nxv2i1,ch = CopyFromReg t0, Register:nxv2i1 %2
        t11: nxv2i32 = splat_vector Constant:i32<1>
      t20: nxv2i32 = add t19, t11
    t21: nxv2i32 = vselect t6, t20, t19
  t17: ch,glue = CopyToReg t0, Register:nxv2i32 $v8, t21
    t2: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %0
  t19: nxv2i32 = freeze t2
  t18: ch = RISCVISD::RET_GLUE t17, Register:nxv2i32 $v8, t17:1



Type-legalized selection DAG: %bb.0 'add:'
SelectionDAG has 13 nodes:
  t0: ch,glue = EntryToken
      t6: nxv2i1,ch = CopyFromReg t0, Register:nxv2i1 %2
        t11: nxv2i32 = splat_vector Constant:i64<1>
      t20: nxv2i32 = add t19, t11
    t21: nxv2i32 = vselect t6, t20, t19
  t17: ch,glue = CopyToReg t0, Register:nxv2i32 $v8, t21
    t2: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %0
  t19: nxv2i32 = freeze t2
  t18: ch = RISCVISD::RET_GLUE t17, Register:nxv2i32 $v8, t17:1
```

Hence why the tests are in that zext form, since they get created during vector legalization. But the zext form only allows us to choose constants of zero or one.

https://github.com/llvm/llvm-project/pull/87338