[llvm] [RISCV] Add patterns for fixed vector vwsll (PR #87316)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 2 00:09:14 PDT 2024
================
@@ -3287,24 +3287,25 @@ bool RISCVDAGToDAGISel::selectVSplatUimm(SDValue N, unsigned Bits,
}
bool RISCVDAGToDAGISel::selectLow8BitsVSplat(SDValue N, SDValue &SplatVal) {
- // Truncates are custom lowered during legalization.
- auto IsTrunc = [this](SDValue N) {
- if (N->getOpcode() != RISCVISD::TRUNCATE_VECTOR_VL)
+ auto IsExtOrTrunc = [](SDValue N) {
+ switch (N->getOpcode()) {
+ case ISD::SIGN_EXTEND:
+ case ISD::ZERO_EXTEND:
+ // There's no passthru on these _VL nodes so any VL/mask is ok, since any
+ // inactive elements will be undef.
+ case RISCVISD::TRUNCATE_VECTOR_VL:
+ case RISCVISD::VSEXT_VL:
+ case RISCVISD::VZEXT_VL:
+ return true;
+ default:
return false;
- SDValue VL;
- selectVLOp(N->getOperand(2), VL);
- // Any vmset_vl is ok, since any bits past VL are undefined and we can
- // assume they are set.
- return N->getOperand(1).getOpcode() == RISCVISD::VMSET_VL &&
- isa<ConstantSDNode>(VL) &&
- cast<ConstantSDNode>(VL)->getSExtValue() == RISCV::VLMaxSentinel;
+ }
+ return true;
----------------
topperc wrote:
This retun is unreachable
https://github.com/llvm/llvm-project/pull/87316
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