[llvm] [RISCV] Add patterns for fixed vector vwsll (PR #87316)

[Craig Topper via llvm-commits]

================
@@ -3287,22 +3287,25 @@ bool RISCVDAGToDAGISel::selectVSplatUimm(SDValue N, unsigned Bits,
 }
 
 bool RISCVDAGToDAGISel::selectLow8BitsVSplat(SDValue N, SDValue &SplatVal) {
-  // Truncates are custom lowered during legalization.
-  auto IsTrunc = [this](SDValue N) {
-    if (N->getOpcode() != RISCVISD::TRUNCATE_VECTOR_VL)
+  auto IsVLNode = [this](SDValue N) {
+    switch (N->getOpcode()) {
+    case RISCVISD::TRUNCATE_VECTOR_VL:
+    case RISCVISD::VSEXT_VL:
+    case RISCVISD::VZEXT_VL:
+      break;
+    default:
       return false;
+    }
     SDValue VL;
----------------
topperc wrote:

Do we still need to select VL is we aren't going to use VL?

https://github.com/llvm/llvm-project/pull/87316